2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
27 #if CONFIG_LOGICAL_CPUS==1
28 #include <cpu/amd/quadcore.h>
31 #include <cpu/amd/amdfam10_sysconf.h>
34 #include "mb_sysconf.h"
36 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
37 struct mb_sysconf_t mb_sysconf;
39 /* Here you only need to set value in pci1234 for HT-IO that could be
40 installed or not You may need to preset pci1234 for HTIO board, please
41 refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */
42 static u32 pci1234x[] = {
43 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
44 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
45 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
46 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
47 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
52 /* HT Chain device num, actually it is unit id base of every ht device
53 in chain, assume every chain only have 4 ht device at most */
55 static unsigned hcdnx[] = {
56 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
57 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
58 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
59 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
60 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
61 0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
62 0x20202020, 0x20202020,
67 extern void get_pci1234(void);
69 static unsigned get_bus_conf_done = 0;
71 void get_bus_conf(void)
75 struct mb_sysconf_t *m;
80 if(get_bus_conf_done==1) return; //do it only once
82 get_bus_conf_done = 1;
84 sysconf.mb = &mb_sysconf;
87 memset(m, 0, sizeof(struct mb_sysconf_t));
89 sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
90 for(i=0;i<sysconf.hc_possible_num; i++) {
91 sysconf.pci1234[i] = pci1234x[i];
92 sysconf.hcdn[i] = hcdnx[i];
97 m->bus_type[0] = 1; //pci
98 sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
99 m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
101 m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff;
102 sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
105 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
108 m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
111 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
115 dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
117 m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
120 printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
126 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3, 0));
127 m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
128 m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
132 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0));
133 m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
134 m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
137 for(i=0; i< sysconf.hc_possible_num; i++) {
138 if(!(sysconf.pci1234[i] & 0x1) ) continue;
140 unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
141 unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
142 for (j = busn; j <= busn_max; j++)
144 if(m->bus_isa <= busn_max)
145 m->bus_isa = busn_max + 1;
146 printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
149 /*I/O APICs: APIC ID Version State Address*/
150 #if CONFIG_LOGICAL_CPUS==1
151 apicid_base = get_apicid_base(3);
153 apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
155 m->apicid_mcp55 = apicid_base+0;
156 m->apicid_8132_1 = apicid_base+1;
157 m->apicid_8132_2 = apicid_base+2;