2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef _PLATFORM_CFG_H_
21 #define _PLATFORM_CFG_H_
24 /* northbridge customize options */
26 * Max number of northbridges in the system
28 #define MAX_NB_COUNT 1 //TODO: only 1 NB tested
31 * Enable check for PCIe endpoint to be ready for PCI enumeration.
34 //#define EPREADY_WORKAROUND_DISABLED
37 * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
40 #define IOMMU_SUPPORT_DISABLE //TODO: enable it
43 * Disable server PCIe hotplug support.
46 //#define HOTPLUG_SUPPORT_DISABLED
49 * Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
52 //#define DEVICE_REMAP_DISABLE
54 #endif //_PLATFORM_CFG_H_