2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
26 "H8QGI ", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
40 Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
42 Name(HPBA, 0xFED00000) /* Base address of HPET table */
43 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
45 /* USB overcurrent mapping pins. */
57 /* Some global data */
58 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
59 Name(OSV, Ones) /* Assume nothing */
60 Name(PMOD, One) /* Assume APIC */
66 Scope (\_PR) { /* define processor scope */
68 P000, /* name space name */
69 0x00, /* Unique number for this processor */
70 0x810, /* PBLK system I/O address !hardcoded! */
71 0x06 /* PBLKLEN for boot processor */
73 //#include "acpi/cpstate.asl"
75 Processor(P001, 0x01, 0x00000000, 0x00) {}
76 Processor(P002, 0x02, 0x00000000, 0x00) {}
77 Processor(P003, 0x03, 0x00000000, 0x00) {}
78 Processor(P004, 0x04, 0x00000000, 0x00) {}
79 Processor(P005, 0x05, 0x00000000, 0x00) {}
80 Processor(P006, 0x06, 0x00000000, 0x00) {}
81 Processor(P007, 0x07, 0x00000000, 0x00) {}
82 Processor(P008, 0x08, 0x00000000, 0x00) {}
83 Processor(P009, 0x09, 0x00000000, 0x00) {}
84 Processor(P00A, 0x0A, 0x00000000, 0x00) {}
85 Processor(P00B, 0x0B, 0x00000000, 0x00) {}
86 Processor(P00C, 0x0C, 0x00000000, 0x00) {}
87 Processor(P00D, 0x0D, 0x00000000, 0x00) {}
88 Processor(P00E, 0x0E, 0x00000000, 0x00) {}
89 Processor(P00F, 0x0F, 0x00000000, 0x00) {}
90 Processor(P010, 0x10, 0x00000000, 0x00) {}
91 Processor(P011, 0x11, 0x00000000, 0x00) {}
92 Processor(P012, 0x12, 0x00000000, 0x00) {}
93 Processor(P013, 0x13, 0x00000000, 0x00) {}
94 Processor(P014, 0x14, 0x00000000, 0x00) {}
95 Processor(P015, 0x15, 0x00000000, 0x00) {}
96 Processor(P016, 0x16, 0x00000000, 0x00) {}
97 Processor(P017, 0x17, 0x00000000, 0x00) {}
98 Processor(P018, 0x18, 0x00000000, 0x00) {}
99 Processor(P019, 0x19, 0x00000000, 0x00) {}
100 Processor(P01A, 0x1A, 0x00000000, 0x00) {}
101 Processor(P01B, 0x1B, 0x00000000, 0x00) {}
102 Processor(P01C, 0x1C, 0x00000000, 0x00) {}
103 Processor(P01D, 0x1D, 0x00000000, 0x00) {}
104 Processor(P01E, 0x1E, 0x00000000, 0x00) {}
105 Processor(P01F, 0x1F, 0x00000000, 0x00) {}
106 Processor(P020, 0x20, 0x00000000, 0x00) {}
107 Processor(P021, 0x21, 0x00000000, 0x00) {}
108 Processor(P022, 0x22, 0x00000000, 0x00) {}
109 Processor(P023, 0x23, 0x00000000, 0x00) {}
110 Processor(P024, 0x24, 0x00000000, 0x00) {}
111 Processor(P025, 0x25, 0x00000000, 0x00) {}
112 Processor(P026, 0x26, 0x00000000, 0x00) {}
113 Processor(P027, 0x27, 0x00000000, 0x00) {}
114 Processor(P028, 0x28, 0x00000000, 0x00) {}
115 Processor(P029, 0x29, 0x00000000, 0x00) {}
116 Processor(P02A, 0x2A, 0x00000000, 0x00) {}
117 Processor(P02B, 0x2B, 0x00000000, 0x00) {}
118 Processor(P02C, 0x2C, 0x00000000, 0x00) {}
119 Processor(P02D, 0x2D, 0x00000000, 0x00) {}
120 Processor(P02E, 0x2E, 0x00000000, 0x00) {}
121 Processor(P02F, 0x2F, 0x00000000, 0x00) {}
131 } /* End _PR scope */
133 /* PIC IRQ mapping registers, C00h-C01h */
134 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
135 Field(PRQM, ByteAcc, NoLock, Preserve) {
137 PRQD, 0x00000008, /* Offset: 1h */
139 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
140 PINA, 0x00000008, /* Index 0 */
141 PINB, 0x00000008, /* Index 1 */
142 PINC, 0x00000008, /* Index 2 */
143 PIND, 0x00000008, /* Index 3 */
144 AINT, 0x00000008, /* Index 4 */
145 SINT, 0x00000008, /* Index 5 */
146 , 0x00000008, /* Index 6 */
147 AAUD, 0x00000008, /* Index 7 */
148 AMOD, 0x00000008, /* Index 8 */
149 PINE, 0x00000008, /* Index 9 */
150 PINF, 0x00000008, /* Index A */
151 PING, 0x00000008, /* Index B */
152 PINH, 0x00000008, /* Index C */
155 /* PCI Error control register */
156 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
157 Field(PERC, ByteAcc, NoLock, Preserve) {
164 /* Client Management index/data registers */
165 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
166 Field(CMT, ByteAcc, NoLock, Preserve) {
168 /* Client Management Data register */
176 /* GPM Port register */
177 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
178 Field(GPT, ByteAcc, NoLock, Preserve) {
189 /* Flash ROM program enable register */
190 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
191 Field(FRE, ByteAcc, NoLock, Preserve) {
196 /* PM2 index/data registers */
197 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
198 Field(PM2R, ByteAcc, NoLock, Preserve) {
203 /* Power Management I/O registers */
204 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
205 Field(PIOR, ByteAcc, NoLock, Preserve) {
209 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
210 Offset(0x00), /* MiscControl */
214 Offset(0x01), /* MiscStatus */
218 Offset(0x04), /* SmiWakeUpEventEnable3 */
221 Offset(0x07), /* SmiWakeUpEventStatus3 */
224 Offset(0x10), /* AcpiEnable */
227 Offset(0x1C), /* ProgramIoEnable */
234 Offset(0x1D), /* IOMonitorStatus */
241 Offset(0x20), /* AcpiPmEvtBlk */
243 Offset(0x36), /* GEvtLevelConfig */
247 Offset(0x37), /* GPMLevelConfig0 */
254 Offset(0x38), /* GPMLevelConfig1 */
261 Offset(0x3B), /* PMEStatus1 */
270 Offset(0x55), /* SoftPciRst */
278 /* Offset(0x61), */ /* Options_1 */
282 Offset(0x65), /* UsbPMControl */
285 Offset(0x68), /* MiscEnable68 */
289 Offset(0x92), /* GEVENTIN */
292 Offset(0x96), /* GPM98IN */
295 Offset(0x9A), /* EnhanceControl */
298 Offset(0xA8), /* PIO7654Enable */
303 Offset(0xA9), /* PIO7654Status */
311 * First word is PM1_Status, Second word is PM1_Enable
313 OperationRegion(P1EB, SystemIO, APEB, 0x04)
314 Field(P1EB, ByteAcc, NoLock, Preserve) {
338 OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
339 Field (GRAM, ByteAcc, Lock, Preserve)
346 /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
347 OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
348 Field(PCFG, ByteAcc, NoLock, Preserve) {
349 /* Byte offsets are computed using the following technique:
350 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
351 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
353 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
355 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
366 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
369 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
371 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
373 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
375 P92E, 1, /* Port92 decode enable */
378 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
379 Field(SB5, AnyAcc, NoLock, Preserve){
381 Offset(0x120), /* Port 0 Task file status */
387 Offset(0x128), /* Port 0 Serial ATA status */
391 Offset(0x12C), /* Port 0 Serial ATA control */
393 Offset(0x130), /* Port 0 Serial ATA error */
398 offset(0x1A0), /* Port 1 Task file status */
404 Offset(0x1A8), /* Port 1 Serial ATA status */
408 Offset(0x1AC), /* Port 1 Serial ATA control */
410 Offset(0x1B0), /* Port 1 Serial ATA error */
415 Offset(0x220), /* Port 2 Task file status */
421 Offset(0x228), /* Port 2 Serial ATA status */
425 Offset(0x22C), /* Port 2 Serial ATA control */
427 Offset(0x230), /* Port 2 Serial ATA error */
432 Offset(0x2A0), /* Port 3 Task file status */
438 Offset(0x2A8), /* Port 3 Serial ATA status */
442 Offset(0x2AC), /* Port 3 Serial ATA control */
444 Offset(0x2B0), /* Port 3 Serial ATA error */
450 #include "acpi/routing.asl"
454 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
455 if(CondRefOf(\_OSI,Local1))
457 Store(1, OSTP) /* Assume some form of XP */
458 if (\_OSI("Windows 2006")) /* Vista */
463 If(WCMP(\_OS,"Linux")) {
464 Store(3, OSTP) /* Linux */
466 Store(4, OSTP) /* Gotta be WinCE */
472 Method(_PIC, 0x01, NotSerialized)
480 Method(CIRQ, 0x00, NotSerialized){
491 Name(IRQB, ResourceTemplate(){
492 IRQ(Level,ActiveLow,Shared){15}
495 Name(IRQP, ResourceTemplate(){
496 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
499 Name(PITF, ResourceTemplate(){
500 IRQ(Level,ActiveLow,Exclusive){9}
504 Name(_HID, EISAID("PNP0C0F"))
509 Return(0x0B) /* sata is invisible */
511 Return(0x09) /* sata is disabled */
513 } /* End Method(_SB.INTA._STA) */
516 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
518 } /* End Method(_SB.INTA._DIS) */
521 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
523 } /* Method(_SB.INTA._PRS) */
526 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
527 CreateWordField(IRQB, 0x1, IRQN)
528 ShiftLeft(1, PINA, IRQN)
530 } /* Method(_SB.INTA._CRS) */
533 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
534 CreateWordField(ARG0, 1, IRQM)
536 /* Use lowest available IRQ */
537 FindSetRightBit(IRQM, Local0)
542 } /* End Method(_SB.INTA._SRS) */
543 } /* End Device(INTA) */
546 Name(_HID, EISAID("PNP0C0F"))
551 Return(0x0B) /* sata is invisible */
553 Return(0x09) /* sata is disabled */
555 } /* End Method(_SB.INTB._STA) */
558 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
560 } /* End Method(_SB.INTB._DIS) */
563 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
565 } /* Method(_SB.INTB._PRS) */
568 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
569 CreateWordField(IRQB, 0x1, IRQN)
570 ShiftLeft(1, PINB, IRQN)
572 } /* Method(_SB.INTB._CRS) */
575 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
576 CreateWordField(ARG0, 1, IRQM)
578 /* Use lowest available IRQ */
579 FindSetRightBit(IRQM, Local0)
584 } /* End Method(_SB.INTB._SRS) */
585 } /* End Device(INTB) */
588 Name(_HID, EISAID("PNP0C0F"))
593 Return(0x0B) /* sata is invisible */
595 Return(0x09) /* sata is disabled */
597 } /* End Method(_SB.INTC._STA) */
600 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
602 } /* End Method(_SB.INTC._DIS) */
605 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
607 } /* Method(_SB.INTC._PRS) */
610 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
611 CreateWordField(IRQB, 0x1, IRQN)
612 ShiftLeft(1, PINC, IRQN)
614 } /* Method(_SB.INTC._CRS) */
617 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
618 CreateWordField(ARG0, 1, IRQM)
620 /* Use lowest available IRQ */
621 FindSetRightBit(IRQM, Local0)
626 } /* End Method(_SB.INTC._SRS) */
627 } /* End Device(INTC) */
630 Name(_HID, EISAID("PNP0C0F"))
635 Return(0x0B) /* sata is invisible */
637 Return(0x09) /* sata is disabled */
639 } /* End Method(_SB.INTD._STA) */
642 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
644 } /* End Method(_SB.INTD._DIS) */
647 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
649 } /* Method(_SB.INTD._PRS) */
652 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
653 CreateWordField(IRQB, 0x1, IRQN)
654 ShiftLeft(1, PIND, IRQN)
656 } /* Method(_SB.INTD._CRS) */
659 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
660 CreateWordField(ARG0, 1, IRQM)
662 /* Use lowest available IRQ */
663 FindSetRightBit(IRQM, Local0)
668 } /* End Method(_SB.INTD._SRS) */
669 } /* End Device(INTD) */
672 Name(_HID, EISAID("PNP0C0F"))
677 Return(0x0B) /* sata is invisible */
679 Return(0x09) /* sata is disabled */
681 } /* End Method(_SB.INTE._STA) */
684 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
686 } /* End Method(_SB.INTE._DIS) */
689 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
691 } /* Method(_SB.INTE._PRS) */
694 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
695 CreateWordField(IRQB, 0x1, IRQN)
696 ShiftLeft(1, PINE, IRQN)
698 } /* Method(_SB.INTE._CRS) */
701 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
702 CreateWordField(ARG0, 1, IRQM)
704 /* Use lowest available IRQ */
705 FindSetRightBit(IRQM, Local0)
710 } /* End Method(_SB.INTE._SRS) */
711 } /* End Device(INTE) */
714 Name(_HID, EISAID("PNP0C0F"))
719 Return(0x0B) /* sata is invisible */
721 Return(0x09) /* sata is disabled */
723 } /* End Method(_SB.INTF._STA) */
726 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
728 } /* End Method(_SB.INTF._DIS) */
731 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
733 } /* Method(_SB.INTF._PRS) */
736 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
737 CreateWordField(IRQB, 0x1, IRQN)
738 ShiftLeft(1, PINF, IRQN)
740 } /* Method(_SB.INTF._CRS) */
743 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
744 CreateWordField(ARG0, 1, IRQM)
746 /* Use lowest available IRQ */
747 FindSetRightBit(IRQM, Local0)
752 } /* End Method(_SB.INTF._SRS) */
753 } /* End Device(INTF) */
756 Name(_HID, EISAID("PNP0C0F"))
761 Return(0x0B) /* sata is invisible */
763 Return(0x09) /* sata is disabled */
765 } /* End Method(_SB.INTG._STA) */
768 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
770 } /* End Method(_SB.INTG._DIS) */
773 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
775 } /* Method(_SB.INTG._CRS) */
778 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
779 CreateWordField(IRQB, 0x1, IRQN)
780 ShiftLeft(1, PING, IRQN)
782 } /* Method(_SB.INTG._CRS) */
785 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
786 CreateWordField(ARG0, 1, IRQM)
788 /* Use lowest available IRQ */
789 FindSetRightBit(IRQM, Local0)
794 } /* End Method(_SB.INTG._SRS) */
795 } /* End Device(INTG) */
798 Name(_HID, EISAID("PNP0C0F"))
803 Return(0x0B) /* sata is invisible */
805 Return(0x09) /* sata is disabled */
807 } /* End Method(_SB.INTH._STA) */
810 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
812 } /* End Method(_SB.INTH._DIS) */
815 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
817 } /* Method(_SB.INTH._CRS) */
820 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
821 CreateWordField(IRQB, 0x1, IRQN)
822 ShiftLeft(1, PINH, IRQN)
824 } /* Method(_SB.INTH._CRS) */
827 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
828 CreateWordField(ARG0, 1, IRQM)
830 /* Use lowest available IRQ */
831 FindSetRightBit(IRQM, Local0)
836 } /* End Method(_SB.INTH._SRS) */
837 } /* End Device(INTH) */
839 } /* End Scope(_SB) */
842 /* Supported sleep states: */
843 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
845 If (LAnd(SSFG, 0x01)) {
846 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
848 If (LAnd(SSFG, 0x02)) {
849 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
851 If (LAnd(SSFG, 0x04)) {
852 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
854 If (LAnd(SSFG, 0x08)) {
855 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
858 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
860 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
861 Name(CSMS, 0) /* Current System State */
863 /* Wake status package */
864 Name(WKST,Package(){Zero, Zero})
867 * \_PTS - Prepare to Sleep method
870 * Arg0=The value of the sleeping state S1=1, S2=2, etc
875 * The _PTS control method is executed at the beginning of the sleep process
876 * for S1-S5. The sleeping value is passed to the _PTS control method. This
877 * control method may be executed a relatively long time before entering the
878 * sleep state and the OS may abort the operation without notification to
879 * the ACPI driver. This method cannot modify the configuration or power
880 * state of any device in the system.
883 /* DBGO("\\_PTS\n") */
884 /* DBGO("From S0 to S") */
888 /* Don't allow PCIRST# to reset USB */
893 /* Clear sleep SMI status flag and enable sleep SMI trap. */
897 /* On older chips, clear PciExpWakeDisEn */
898 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
903 /* Clear wake status structure. */
904 Store(0, Index(WKST,0))
905 Store(0, Index(WKST,1))
906 \_SB.PCI0.SIOS (Arg0)
907 } /* End Method(\_PTS) */
910 * The following method results in a "not a valid reserved NameSeg"
911 * warning so I have commented it out for the duration. It isn't
912 * used, so it could be removed.
915 * \_GTS OEM Going To Sleep method
918 * Arg0=The value of the sleeping state S1=1, S2=2
925 * DBGO("From S0 to S")
932 * \_BFS OEM Back From Sleep method
935 * Arg0=The value of the sleeping state S1=1, S2=2
941 /* DBGO("\\_BFS\n") */
944 /* DBGO(" to S0\n") */
948 * \_WAK System Wake method
951 * Arg0=The value of the sleeping state S1=1, S2=2
954 * Return package of 2 DWords
956 * 0x00000000 wake succeeded
957 * 0x00000001 Wake was signaled but failed due to lack of power
958 * 0x00000002 Wake was signaled but failed due to thermal condition
959 * Dword 2 - Power Supply state
960 * if non-zero the effective S-state the power supply entered
963 /* DBGO("\\_WAK\n") */
966 /* DBGO(" to S0\n") */
971 /* Restore PCIRST# so it resets USB */
976 /* Arbitrarily clear PciExpWakeStatus */
979 /* if(DeRefOf(Index(WKST,0))) {
980 * Store(0, Index(WKST,1))
982 * Store(Arg0, Index(WKST,1))
985 \_SB.PCI0.SIOW (Arg0)
987 } /* End Method(\_WAK) */
989 Scope(\_GPE) { /* Start Scope GPE */
990 /* General event 0 */
992 //DBGO("\\_GPE\\_L00\n")
995 /* General event 1 */
997 //DBGO("\\_GPE\\_L01\n")
1000 /* General event 2 */
1002 //DBGO("\\_GPE\\_L02\n")
1005 /* General event 3 */
1007 //DBGO("\\_GPE\\_L00\n")
1008 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1011 /* General event 4 */
1013 //DBGO("\\_GPE\\_L04\n")
1016 /* General event 5 */
1018 //DBGO("\\_GPE\\_L05\n")
1021 /* _L06 General event 6 - Used for GPM6, moved to USB.asl */
1022 /* _L07 General event 7 - Used for GPM7, moved to USB.asl */
1024 /* Legacy PM event */
1026 //DBGO("\\_GPE\\_L08\n")
1029 /* Temp warning (TWarn) event */
1031 //DBGO("\\_GPE\\_L09\n")
1032 Notify (\_TZ.TZ00, 0x80)
1037 //DBGO("\\_GPE\\_L0A\n")
1040 /* USB controller PME# */
1042 //DBGO("\\_GPE\\_L0B\n")
1043 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1044 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1045 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1046 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1047 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1048 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1049 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1052 /* AC97 controller PME# */
1054 //DBGO("\\_GPE\\_L0C\n")
1057 /* OtherTherm PME# */
1059 //DBGO("\\_GPE\\_L0D\n")
1062 /* _L0E GPM9 SCI event - Moved to USB.asl */
1064 /* PCIe HotPlug event */
1066 //DBGO("\\_GPE\\_L0F\n")
1069 /* ExtEvent0 SCI event */
1071 //DBGO("\\_GPE\\_L10\n")
1075 /* ExtEvent1 SCI event */
1077 //DBGO("\\_GPE\\_L11\n")
1080 /* PCIe PME# event */
1082 //DBGO("\\_GPE\\_L12\n")
1085 /* _L13 GPM0 SCI event - Moved to USB.asl */
1086 /* _L14 GPM1 SCI event - Moved to USB.asl */
1087 /* _L15 GPM2 SCI event - Moved to USB.asl */
1088 /* _L16 GPM3 SCI event - Moved to USB.asl */
1089 /* _L17 GPM8 SCI event - Moved to USB.asl */
1091 /* GPIO0 or GEvent8 event */
1093 //DBGO("\\_GPE\\_L18\n")
1094 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1095 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1096 Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
1097 Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
1098 Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
1099 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1102 /* _L19 GPM4 SCI event - Moved to USB.asl */
1103 /* _L1A GPM5 SCI event - Moved to USB.asl */
1105 /* Azalia SCI event */
1107 //DBGO("\\_GPE\\_L1B\n")
1108 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1109 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1112 /* GPM6 SCI event - Reassigned to _L06 */
1114 //DBGO("\\_GPE\\_L1C\n")
1117 /* GPM7 SCI event - Reassigned to _L07 */
1119 //DBGO("\\_GPE\\_L1D\n")
1122 /* GPIO2 or GPIO66 SCI event */
1124 //DBGO("\\_GPE\\_L1E\n")
1127 /* _L1F SATA SCI event - Moved to sata.asl */
1129 } /* End Scope GPE */
1131 #include "acpi/usb.asl"
1134 Scope(\_SB) { /* Start \_SB scope */
1135 #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1138 /* Note: Only need HID on Primary Bus */
1140 External (TOM1) //assigned when update_ssdt()
1141 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1143 Name(_HID, EISAID("PNP0A03"))
1144 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1145 Method(_BBN, 0) { /* Bus number = 0 */
1149 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1150 Return(0x0B) /* Status is visible */
1154 If(PMOD){ Return(APR0) } /* APIC mode */
1155 Return (PR0) /* PIC Mode */
1158 /* Describe the Northbridge devices */
1160 Name(_ADR, 0x00000000)
1163 /* The external GFX bridge */
1165 Name(_ADR, 0x00020000)
1166 Name(_PRW, Package() {0x18, 4})
1168 If(PMOD){ Return(APS2) } /* APIC mode */
1169 Return (PS2) /* PIC Mode */
1173 /* Dev3 is also an external GFX bridge */
1176 Name(_ADR, 0x00040000)
1177 Name(_PRW, Package() {0x18, 4})
1179 If(PMOD){ Return(APS4) } /* APIC mode */
1180 Return (PS4) /* PIC Mode */
1185 Name(_ADR, 0x000b0000)
1186 Name(_PRW, Package() {0x18, 4})
1188 If(PMOD){ Return(APSb) } /* APIC mode */
1189 Return (PSb) /* PIC Mode */
1194 Name(_ADR, 0x000c0000)
1195 Name(_PRW, Package() {0x18, 4})
1197 If(PMOD){ Return(APSc) } /* APIC mode */
1198 Return (PSc) /* PIC Mode */
1203 Name(_ADR, 0x000d0000)
1204 Name(_PRW, Package() {0x18, 4})
1206 If(PMOD){ Return(APSd) } /* APIC mode */
1207 Return (PSd) /* PIC Mode */
1211 /* Describe the Southbridge devices */
1213 Name(_ADR, 0x00110000)
1214 #include "acpi/sata.asl"
1218 Name(_ADR, 0x00130000)
1219 Name(_PRW, Package() {0x0B, 3})
1223 Name(_ADR, 0x00130001)
1224 Name(_PRW, Package() {0x0B, 3})
1228 Name(_ADR, 0x00130002)
1229 Name(_PRW, Package() {0x0B, 3})
1233 Name(_ADR, 0x00130003)
1234 Name(_PRW, Package() {0x0B, 3})
1238 Name(_ADR, 0x00130004)
1239 Name(_PRW, Package() {0x0B, 3})
1243 Name(_ADR, 0x00130005)
1244 Name(_PRW, Package() {0x0B, 3})
1248 Name(_ADR, 0x00140000)
1251 /* Primary (and only) IDE channel */
1253 Name(_ADR, 0x00140001)
1254 #include "acpi/ide.asl"
1258 Name(_ADR, 0x00140002)
1259 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1260 Field(AZPD, AnyAcc, NoLock, Preserve) {
1284 If(LEqual(OSTP,3)){ /* If we are running Linux */
1293 Name(_ADR, 0x00140003)
1295 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1296 } */ /* End Method(_SB.SBRDG._INI) */
1298 /* Real Time Clock Device */
1300 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1301 Name(_CRS, ResourceTemplate() {
1303 IO(Decode16,0x0070, 0x0070, 0, 2)
1304 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1306 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1308 Device(TMR) { /* Timer */
1309 Name(_HID,EISAID("PNP0100")) /* System Timer */
1310 Name(_CRS, ResourceTemplate() {
1312 IO(Decode16, 0x0040, 0x0040, 0, 4)
1313 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1315 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1317 Device(SPKR) { /* Speaker */
1318 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1319 Name(_CRS, ResourceTemplate() {
1320 IO(Decode16, 0x0061, 0x0061, 0, 1)
1322 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1325 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1326 Name(_CRS, ResourceTemplate() {
1328 IO(Decode16,0x0020, 0x0020, 0, 2)
1329 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1330 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1331 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1333 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1335 Device(MAD) { /* 8257 DMA */
1336 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1337 Name(_CRS, ResourceTemplate() {
1338 DMA(Compatibility,BusMaster,Transfer8){4}
1339 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1340 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1341 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1342 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1343 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1344 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1345 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1346 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1349 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1350 Name(_CRS, ResourceTemplate() {
1351 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1354 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1357 Name (_HID, EisaId ("PNP0F13"))
1358 Name (_CRS, ResourceTemplate () {
1359 IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
1360 IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
1363 Method (_STA, 0, NotSerialized) {
1364 And (FLG0, 0x04, Local0)
1365 If (LEqual (Local0, 0x04)) {
1374 Name (_HID, EisaId ("PNP0303"))
1375 Method (_STA, 0, NotSerialized) {
1376 And (FLG0, 0x04, Local0)
1377 If (LEqual (Local0, 0x04)) {
1383 Name (_CRS, ResourceTemplate () {
1384 IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
1385 IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
1390 #if 0 //acpi_create_hpet
1392 Name(_HID,EISAID("PNP0103"))
1393 Name(CRS, ResourceTemplate() {
1397 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT) /* 1kb reserved space */
1399 Method(_STA, 0, NotSerialized) {
1400 Return(0x0F) /* sata is visible */
1402 Method(_CRS, 0, NotSerialized) {
1403 CreateDwordField(CRS, ^MNT._BAS, HPT)
1407 } /* End Device(_SB.PCI0.LIBR.HPET) */
1412 Name(_ADR, 0x00140004)
1413 } /* end HostPciBr */
1416 Name(_ADR, 0x00140005)
1417 } /* end Ac97audio */
1420 Name(_ADR, 0x00140006)
1421 } /* end Ac97modem */
1423 /* ITE8718 Support */
1424 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1425 Field (IOID, ByteAcc, NoLock, Preserve)
1427 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1430 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1433 LDN, 8, /* Logical Device Number */
1435 CID1, 8, /* Chip ID Byte 1, 0x87 */
1436 CID2, 8, /* Chip ID Byte 2, 0x12 */
1438 ACTR, 8, /* Function activate */
1440 APC0, 8, /* APC/PME Event Enable Register */
1441 APC1, 8, /* APC/PME Status Register */
1442 APC2, 8, /* APC/PME Control Register 1 */
1443 APC3, 8, /* Environment Controller Special Configuration Register */
1444 APC4, 8 /* APC/PME Control Register 2 */
1447 /* Enter the 8718 MB PnP Mode */
1453 Store(0x55, SIOI) /* 8718 magic number */
1455 /* Exit the 8718 MB PnP Mode */
1462 * Keyboard PME is routed to SB700 Gevent3. We can wake
1463 * up the system by pressing the key.
1467 /* We only enable KBD PME for S5. */
1468 If (LLess (Arg0, 0x05))
1471 /* DBGO("8718F\n") */
1474 Store (One, ACTR) /* Enable EC */
1478 */ /* falling edge. which mode? Not sure. */
1481 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1483 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1492 Store (Zero, APC0) /* disable keyboard PME */
1494 Store (0xFF, APC1) /* clear keyboard PME status */
1498 Name (CRS, ResourceTemplate ()
1500 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
1501 0x0000, // Granularity
1502 0x0000, // Range Minimum
1503 0x00FF, // Range Maximum
1504 0x0000, // Translation Offset
1508 0x0CF8, // Range Minimum
1509 0x0CF8, // Range Maximum
1514 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1515 0x0000, // Granularity
1516 0x0000, // Range Minimum
1517 0x03AF, // Range Maximum
1518 0x0000, // Translation Offset
1521 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1522 0x0000, // Granularity
1523 0x03E0, // Range Minimum
1524 0x0CF7, // Range Maximum
1525 0x0000, // Translation Offset
1529 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1530 0x0000, // Granularity
1531 0x03B0, // Range Minimum
1532 0x03BB, // Range Maximum
1533 0x0000, // Translation Offset
1536 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1537 0x0000, // Granularity
1538 0x03C0, // Range Minimum
1539 0x03DF, // Range Maximum
1540 0x0000, // Translation Offset
1543 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1544 0x0000, // Granularity
1545 0x0D00, // Range Minimum
1546 0xFFFF, // Range Maximum
1547 0x0000, // Translation Offset
1550 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space
1552 Memory32Fixed (ReadOnly,
1553 0xE0000000, // Address Base
1554 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default)
1558 Method (_CRS, 0, NotSerialized)
1560 CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
1561 CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
1564 * Declare memory between TOM1 and 4GB as available
1566 * Use ShiftLeft to avoid 64bit constant (for XP).
1567 * This will work even if the OS does 32bit arithmetic, as
1568 * 32bit (0x00000000 - TOM1) will wrap and give the same
1569 * result as 64bit (0x100000000 - TOM1).
1572 ShiftLeft(0x10000000, 4, Local0)
1573 Subtract(Local0, TOM1, Local0)
1582 * FIRST METHOD CALLED UPON BOOT
1584 * 1. If debugging, print current OS and ACPI interpreter.
1585 * 2. Get PCI Interrupt routing from ACPI VSM, this
1586 * value is based on user choice in BIOS setup.
1589 /* DBGO("\\_SB\\_INI\n") */
1590 /* DBGO(" DSDT.ASL code from ") */
1591 /* DBGO(__DATE__) */
1593 /* DBGO(__TIME__) */
1594 /* DBGO("\n Sleep states supported: ") */
1596 /* DBGO(" \\_OS=") */
1598 /* DBGO("\n \\_REV=") */
1602 /* Determine the OS we're running on */
1604 /* On older chips, clear PciExpWakeDisEn */
1605 /*if (LLessEqual(\SBRI, 0x13)) {
1609 } /* End Method(_SB._INI) */
1610 } /* End Device(PCI0) */
1612 Device(PWRB) { /* Start Power button device */
1613 Name(_HID, EISAID("PNP0C0C"))
1615 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1616 Name(_STA, 0x0B) /* sata is invisible */
1618 } /* End \_SB scope */
1622 /* DBGO("\\_SI\\_SST\n") */
1623 /* DBGO(" New Indicator state: ") */
1627 } /* End Scope SI */
1631 OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1632 Field (SMB0, ByteAcc, NoLock, Preserve) {
1633 HSTS, 8, /* SMBUS status */
1634 SSTS, 8, /* SMBUS slave status */
1635 HCNT, 8, /* SMBUS control */
1636 HCMD, 8, /* SMBUS host cmd */
1637 HADD, 8, /* SMBUS address */
1638 DAT0, 8, /* SMBUS data0 */
1639 DAT1, 8, /* SMBUS data1 */
1640 BLKD, 8, /* SMBUS block data */
1641 SCNT, 8, /* SMBUS slave control */
1642 SCMD, 8, /* SMBUS shaow cmd */
1643 SEVT, 8, /* SMBUS slave event */
1644 SDAT, 8 /* SMBUS slave data */
1647 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1649 Store (0xFA, Local0)
1650 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1658 Method (SWTC, 1, NotSerialized) {
1659 Store (Arg0, Local0)
1660 Store (0x07, Local2)
1662 While (LEqual (Local1, One)) {
1663 Store (And (HSTS, 0x1E), Local3)
1664 If (LNotEqual (Local3, Zero)) { /* read sucess */
1665 If (LEqual (Local3, 0x02)) {
1666 Store (Zero, Local2)
1669 Store (Zero, Local1)
1672 If (LLess (Local0, 0x0A)) { /* read failure */
1673 Store (0x10, Local2)
1674 Store (Zero, Local1)
1677 Sleep (0x0A) /* 10 ms, try again */
1678 Subtract (Local0, 0x0A, Local0)
1686 Method (SMBR, 3, NotSerialized) {
1687 Store (0x07, Local0)
1688 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1689 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1690 If (LEqual (Local0, Zero)) {
1696 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1698 If (LEqual (Arg0, 0x07)) {
1699 Store (0x48, HCNT) /* read byte */
1702 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1703 If (LEqual (Local1, Zero)) {
1704 If (LEqual (Arg0, 0x07)) {
1705 Store (DAT0, Local0)
1709 Store (Local1, Local0)
1715 /* DBGO("the value of SMBusData0 register ") */
1731 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1732 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1733 Return(Add(0, 2730))
1735 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1736 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1737 Return(Package() {\_TZ.TZ00.FAN0})
1740 Name(_HID, EISAID("PNP0C0B"))
1741 Name(_PR0, Package() {PFN0})
1744 PowerResource(PFN0,0,0) {
1750 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1753 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1757 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1758 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1759 Return (Add (THOT, KELV))
1761 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1762 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1763 Return (Add (TCRT, KELV))
1765 Method(_TMP,0) { /* return current temp of this zone */
1766 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1767 If (LGreater (Local0, 0x10)) {
1768 Store (Local0, Local1)
1771 Add (Local0, THOT, Local0)
1772 Return (Add (400, KELV))
1775 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1776 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1777 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1778 If (LGreater (Local0, 0x10)) {
1779 If (LGreater (Local0, Local1)) {
1780 Store (Local0, Local1)
1783 Multiply (Local1, 10, Local1)
1784 Return (Add (Local1, KELV))
1787 Add (Local0, THOT, Local0)
1788 Return (Add (400 , KELV))
1794 /* End of ASL file */