src/mainboard/supermicro/h8qgi/devicetree.cb

   1 #
   2 # This file is part of the coreboot project.
   3 #
   4 # Copyright (C) 2011 Advanced Micro Devices, Inc.
   5 #
   6 # This program is free software; you can redistribute it and/or modify
   7 # it under the terms of the GNU General Public License as published by
   8 # the Free Software Foundation; version 2 of the License.
   9 #
  10 # This program is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 # GNU General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU General Public License
  16 # along with this program; if not, write to the Free Software
  17 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 #
  19 chip northbridge/amd/agesa/family10/root_complex
  20         device lapic_cluster 0 on
  21                 chip cpu/amd/agesa/family10
  22                         device lapic 0x10 on end
  23                 end
  24         end
  25         device pci_domain 0 on
  26                 subsystemid 0x15d9 0xab11 inherit #SuperMicro
  27                 chip northbridge/amd/agesa/family10 # CPU side of HT root complex
  28                         device pci 18.0 on end # link 0
  29                         device pci 18.0 on end # link 1
  30                         device pci 18.0 on end # link 2
  31                         device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
  32                                 chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
  33                                         device pci 0.0 on  end # HT Root Complex 0x9600
  34                                         device pci 0.1 off end # CLKCONFIG
  35                                         device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
  36                                         device pci 3.0 off end # GPP1 Port1
  37                                         device pci 4.0 off end # GPP3a Port0  x4 SAS
  38                                         device pci 5.0 off end # GPP3a Port1
  39                                         device pci 6.0 off end # GPP3a Port2
  40                                         device pci 7.0 off end # GPP3a Port3
  41                                         device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
  42                                         device pci 9.0 off end # GPP3a Port4  x1 NC
  43                                         device pci a.0 off end # GPP3a Port5  x1 NC
  44                                         device pci b.0 off end # GPP2 Port0 (Not for sr5650)
  45                                         device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
  46                                         device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
  47                                         register "gpp1_configuration" = "0"   # Configuration 16:0 default
  48                                         register "gpp2_configuration" = "1"   # Configuration 8:8
  49                                         register "gpp3a_configuration" = "2"   # Configuration 4:1:1:0:0:0
  50                                         #register "gpp3a_configuration" = "11"   # Configuration 1:1:1:1:1:1
  51                                         register "port_enable" = "0x2104"
  52                                 end #southbridge/amd/sr5650
  53                                 chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
  54                                         device pci 11.0 on end # SATA
  55                                         device pci 12.0 on end # USB1
  56                                         device pci 12.1 on end # USB1
  57                                         device pci 12.2 on end # USB1
  58                                         device pci 13.0 on end # USB2
  59                                         device pci 13.1 on end # USB2
  60                                         device pci 13.2 on end # USB2
  61                                         device pci 14.0 on end # SM
  62                                         device pci 14.1 on end # IDE  0x439c
  63                                         device pci 14.2 off end # HDA  0x4383, h8qgi doesnt have codec.
  64                                         device pci 14.3 on # LPC  0x439d
  65                                                 chip superio/winbond/w83627dhg
  66                                                         device pnp 2e.0 off #  Floppy
  67                                                                 io 0x60 = 0x3f0
  68                                                                 irq 0x70 = 6
  69                                                                 drq 0x74 = 2
  70                                                         end
  71                                                         device pnp 2e.1 off #  Parallel Port
  72                                                                 io 0x60 = 0x378
  73                                                                 irq 0x70 = 7
  74                                                         end
  75                                                         device pnp 2e.2 on  #  Com1
  76                                                                 io 0x60 = 0x3f8
  77                                                                 irq 0x70 = 4
  78                                                         end
  79                                                         device pnp 2e.3 on  #  Com2
  80                                                                 io 0x60 = 0x2f8
  81                                                                 irq 0x70 = 3
  82                                                         end
  83                                                         ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
  84                                                         device pnp 2e.5 on #  PS/2 keyboard & mouse
  85                                                                 io 0x60 = 0x60
  86                                                                 io 0x62 = 0x64
  87                                                                 irq 0x70 = 0x01 #keyboard
  88                                                                 irq 0x72 = 0x0C #mouse
  89                                                         end
  90                                                         #device pnp 2e.6 off #  SPI
  91                                                         #end
  92                                                         device pnp 2e.307 off #  GPIO6
  93                                                         end
  94                                                         device pnp 2e.8 off #  WDTO#, PLED
  95                                                         end
  96                                                         device pnp 2e.009 off #  GPIO2
  97                                                         end
  98                                                         device pnp 2e.109 off #  GPIO3
  99                                                         end
 100                                                         device pnp 2e.209 off #  GPIO4
 101                                                         end
 102                                                         device pnp 2e.309 off #  GPIO5
 103                                                         end
 104                                                         device pnp 2e.a off #  ACPI
 105                                                         end
 106                                                         device pnp 2e.b off # HWM
 107                                                                 io 0x60 = 0x290
 108                                                         end
 109                                                         device pnp 2e.c off # PECI, SST
 110                                                         end
 111                                                 end #superio/winbond/w83627dhg
 112                                         end # LPC
 113                                         device pci 14.4 on end # PCI 0x4384
 114                                         device pci 14.5 on end # USB 3
 115                                         register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
 116                                 end # southbridge/amd/sp5100
 117                         end # device pci 18.0
 118
 119                         device pci 18.1 on end
 120                         device pci 18.2 on end
 121                         device pci 18.3 on end
 122                         device pci 18.4 on end
 123
 124                         device pci 19.0 on end
 125                         device pci 19.1 on end
 126                         device pci 19.2 on end
 127                         device pci 19.3 on end
 128                         device pci 19.4 on end
 129
 130
 131                         device pci 1a.0 on end
 132                         device pci 1a.0 on end
 133                         device pci 1a.0 on end
 134                         device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
 135                         end
 136                         device pci 1a.1 on end
 137                         device pci 1a.2 on end
 138                         device pci 1a.3 on end
 139                         device pci 1a.4 on end
 140
 141                         device pci 1b.0 on end
 142                         device pci 1b.1 on end
 143                         device pci 1b.2 on end
 144                         device pci 1b.3 on end
 145                         device pci 1b.4 on end
 146
 147
 148                         device pci 1c.0 on end
 149                         device pci 1c.1 on end
 150                         device pci 1c.2 on end
 151                         device pci 1c.3 on end
 152                         device pci 1c.4 on end
 153
 154                         device pci 1d.0 on end
 155                         device pci 1d.1 on end
 156                         device pci 1d.2 on end
 157                         device pci 1d.3 on end
 158                         device pci 1d.4 on end
 159
 160
 161                         device pci 1e.0 on end
 162                         device pci 1e.1 on end
 163                         device pci 1e.2 on end
 164                         device pci 1e.3 on end
 165                         device pci 1e.4 on end
 166
 167                         device pci 1f.0 on end
 168                         device pci 1f.1 on end
 169                         device pci 1f.2 on end
 170                         device pci 1f.3 on end
 171                         device pci 1f.4 on end
 172
 173                 end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
 174         end #pci_domain
 175 end #northbridge/amd/agesa/family10/root_complex
 176