2 # This file is part of the coreboot project.
4 # Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
6 # This program is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; version 2 of the License.
10 # This program is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 # GNU General Public License for more details.
15 # You should have received a copy of the GNU General Public License
16 # along with this program; if not, write to the Free Software
17 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 chip northbridge/amd/agesa/family15/root_complex
20 device lapic_cluster 0 on
21 chip cpu/amd/agesa/family15
22 device lapic 0x20 on end #f15
23 #device lapic 0x10 on end #f10
26 device pci_domain 0 on
27 subsystemid 0x15d9 0xab11 inherit #SuperMicro
28 chip northbridge/amd/agesa/family15 # CPU side of HT root complex
29 device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology
30 chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
31 device pci 0.0 on end # HT Root Complex 0x9600
32 device pci 0.1 off end # CLKCONFIG
33 device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16
34 device pci 3.0 off end # GPP1 Port1
35 device pci 4.0 off end # GPP3a Port0 x4 SAS
36 device pci 5.0 off end # GPP3a Port1
37 device pci 6.0 off end # GPP3a Port2
38 device pci 7.0 off end # GPP3a Port3
39 device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
40 device pci 9.0 off end # GPP3a Port4 x1 NC
41 device pci a.0 off end # GPP3a Port5 x1 NC
42 device pci b.0 off end # GPP2 Port0 (Not for sr5650)
43 device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
44 device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
45 register "gpp1_configuration" = "0" # Configuration 16:0 default
46 register "gpp2_configuration" = "1" # Configuration 8:8
47 register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
48 register "port_enable" = "0x2104"
49 end #northbridge/amd/cimx/rd890
50 chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
51 device pci 11.0 on end # SATA
52 device pci 12.0 on end # USB1
53 device pci 12.1 on end # USB1
54 device pci 12.2 on end # USB1
55 device pci 13.0 on end # USB2
56 device pci 13.1 on end # USB2
57 device pci 13.2 on end # USB2
58 device pci 14.0 on end # SM
59 device pci 14.1 off end # IDE 0x439c
60 device pci 14.2 off end # HDA 0x4383, h8qgi not have codec.
61 device pci 14.3 on # LPC 0x439d
62 chip superio/winbond/w83627dhg
63 device pnp 2e.0 off # Floppy
68 device pnp 2e.1 off # Parallel Port
72 device pnp 2e.2 on # Com1
76 device pnp 2e.3 on # Com2
80 ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS##
81 device pnp 2e.5 on # PS/2 keyboard & mouse
84 irq 0x70 = 0x01 #keyboard
85 irq 0x72 = 0x0C #mouse
87 device pnp 2e.6 off # SPI
89 device pnp 2e.307 off # GPIO6
91 device pnp 2e.8 off # WDTO#, PLED
93 device pnp 2e.009 off # GPIO2
95 device pnp 2e.109 off # GPIO3
97 device pnp 2e.209 off # GPIO4
99 device pnp 2e.309 off # GPIO5
101 device pnp 2e.a off # ACPI
103 device pnp 2e.b off # HWM
106 device pnp 2e.c off # PECI, SST
108 end #superio/winbond/w83627dhg
109 chip drivers/i2c/w83795
110 device pnp 5e on #hwm
112 end #drivers/i2c/w83795
114 device pci 14.4 on end # PCI 0x4384
115 device pci 14.5 on end # USB 3
116 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
117 end # southbridge/amd/cimx/sb700
118 end # device pci 18.0
120 device pci 18.1 on end
121 device pci 18.2 on end
122 device pci 18.3 on end
123 device pci 18.4 on end
124 device pci 18.5 on end #f15
125 end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
127 end #northbridge/amd/agesa/family15/root_complex