src/mainboard/supermicro/h8dmr_fam10/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  23 # for testing with -O != s. FIXME
  24 #default CONFIG_XIP_ROM_SIZE = 128 * 1024
  25 default CONFIG_XIP_ROM_SIZE = 128 * 1024
  26 include /config/failovercalculation.lb
  27
  28 arch i386 end
  29
  30 ##
  31 ## Build the objects we have code for in this directory.
  32 ##
  33
  34 driver mainboard.o
  35 #needed by irq_tables and mptable and acpi_tables
  36 object get_bus_conf.o
  37
  38 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  39 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  40 #object reset.o
  41
  42         if CONFIG_USE_INIT
  43                 makerule ./auto.o
  44                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  45                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  46                 end
  47         else
  48                 makerule ./auto.inc
  49                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  50                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  51                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  52                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  53                 end
  54         end
  55
  56 if CONFIG_USE_FAILOVER_IMAGE
  57 else
  58     if CONFIG_AP_CODE_IN_CAR
  59         makerule ./apc_auto.o
  60                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  61                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  62         end
  63     end
  64 end
  65
  66
  67 ##
  68 ## Build our 16 bit and 32 bit coreboot entry code
  69 ##
  70 if CONFIG_HAVE_FAILOVER_BOOT
  71     if CONFIG_USE_FAILOVER_IMAGE
  72         mainboardinit cpu/x86/16bit/entry16.inc
  73         ldscript /cpu/x86/16bit/entry16.lds
  74     end
  75 else
  76     if CONFIG_USE_FALLBACK_IMAGE
  77         mainboardinit cpu/x86/16bit/entry16.inc
  78         ldscript /cpu/x86/16bit/entry16.lds
  79     end
  80 end
  81
  82 mainboardinit cpu/x86/32bit/entry32.inc
  83
  84         if CONFIG_USE_INIT
  85                 ldscript /cpu/x86/32bit/entry32.lds
  86         end
  87
  88         if CONFIG_USE_INIT
  89                 ldscript /cpu/amd/car/cache_as_ram.lds
  90         end
  91
  92 ##
  93 ## Build our reset vector (This is where coreboot is entered)
  94 ##
  95 if CONFIG_HAVE_FAILOVER_BOOT
  96     if CONFIG_USE_FAILOVER_IMAGE
  97         mainboardinit cpu/x86/16bit/reset16.inc
  98         ldscript /cpu/x86/16bit/reset16.lds
  99     else
 100         mainboardinit cpu/x86/32bit/reset32.inc
 101         ldscript /cpu/x86/32bit/reset32.lds
 102     end
 103 else
 104     if CONFIG_USE_FALLBACK_IMAGE
 105         mainboardinit cpu/x86/16bit/reset16.inc
 106         ldscript /cpu/x86/16bit/reset16.lds
 107     else
 108         mainboardinit cpu/x86/32bit/reset32.inc
 109         ldscript /cpu/x86/32bit/reset32.lds
 110     end
 111 end
 112
 113 ##
 114 ## Include an id string (For safe flashing)
 115 ##
 116 mainboardinit southbridge/nvidia/mcp55/id.inc
 117 ldscript /southbridge/nvidia/mcp55/id.lds
 118
 119 ##
 120 ## ROMSTRAP table for MCP55
 121 ##
 122 if CONFIG_HAVE_FAILOVER_BOOT
 123     if CONFIG_USE_FAILOVER_IMAGE
 124         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 125         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 126     end
 127 else
 128     if CONFIG_USE_FALLBACK_IMAGE
 129         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 130         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 131     end
 132 end
 133
 134         ##
 135         ## Setup Cache-As-Ram
 136         ##
 137         mainboardinit cpu/amd/car/cache_as_ram.inc
 138
 139 ###
 140 ### This is the early phase of coreboot startup
 141 ### Things are delicate and we test to see if we should
 142 ### failover to another image.
 143 ###
 144 if CONFIG_HAVE_FAILOVER_BOOT
 145     if CONFIG_USE_FAILOVER_IMAGE
 146                 ldscript /arch/i386/lib/failover_failover.lds
 147     end
 148 else
 149     if CONFIG_USE_FALLBACK_IMAGE
 150                 ldscript /arch/i386/lib/failover.lds
 151     end
 152 end
 153
 154 ##
 155 ## Setup RAM
 156 ##
 157         if CONFIG_USE_INIT
 158                 initobject auto.o
 159         else
 160                 mainboardinit ./auto.inc
 161         end
 162
 163 ##
 164 ## Include the secondary Configuration files
 165 ##
 166 config chip.h
 167
 168 dir /southbridge/nvidia/mcp55
 169
 170 chip northbridge/amd/amdfam10/root_complex
 171         device apic_cluster 0 on
 172                 chip cpu/amd/socket_F_1207
 173                         device apic 0 on end
 174                 end
 175         end
 176         device pci_domain 0 on
 177                 chip northbridge/amd/amdfam10 #mc0
 178                         device pci 18.0 on end
 179                         device pci 18.0 on end
 180                         device pci 18.0 on
 181         # SB on link 2.0
 182                                 chip southbridge/nvidia/mcp55
 183                                         device pci 0.0 on end   # HT
 184                                         device pci 1.0 on # LPC
 185                                                 chip superio/winbond/w83627hf
 186                                                         device pnp 2e.0 off #  Floppy
 187                                                                 io 0x60 = 0x3f0
 188                                                                 irq 0x70 = 6
 189                                                                 drq 0x74 = 2
 190                                                         end
 191                                                         device pnp 2e.1 off #  Parallel Port
 192                                                                 io 0x60 = 0x378
 193                                                                 irq 0x70 = 7
 194                                                         end
 195                                                         device pnp 2e.2 on #  Com1
 196                                                                 io 0x60 = 0x3f8
 197                                                                 irq 0x70 = 4
 198                                                         end
 199                                                         device pnp 2e.3 on #  Com2
 200                                                                 io 0x60 = 0x2f8
 201                                                                 irq 0x70 = 3
 202                                                         end
 203                                                         device pnp 2e.5 on #  Keyboard
 204                                                                 io 0x60 = 0x60
 205                                                                 io 0x62 = 0x64
 206                                                                 irq 0x70 = 1
 207                                                                 irq 0x72 = 12
 208                                                         end
 209                                                         device pnp 2e.6 off  # SFI
 210                                                                 io 0x62 = 0x100
 211                                                         end
 212                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 213                                                                 io 0x60 = 0x220
 214                                                                 io 0x62 = 0x300
 215                                                                 irq 0x70 = 9
 216                                                         end
 217                                                         device pnp 2e.8 off end #  WDTO_PLED
 218                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 219                                                         device pnp 2e.a off end #  ACPI
 220                                                         device pnp 2e.b on #  HW Monitor
 221                                                                 io 0x60 = 0x290
 222                                                                 irq 0x70 = 5
 223                                                         end
 224                                                 end
 225                                         end
 226                                         device pci 1.1 on # SM 0
 227                                                 chip drivers/generic/generic #dimm 0-0-0
 228                                                         device i2c 50 on end
 229                                                 end
 230                                                 chip drivers/generic/generic #dimm 0-0-1
 231                                                         device i2c 51 on end
 232                                                 end
 233                                                 chip drivers/generic/generic #dimm 0-1-0
 234                                                         device i2c 52 on end
 235                                                 end
 236                                                 chip drivers/generic/generic #dimm 0-1-1
 237                                                         device i2c 53 on end
 238                                                 end
 239                                                 chip drivers/generic/generic #dimm 1-0-0
 240                                                         device i2c 54 on end
 241                                                 end
 242                                                 chip drivers/generic/generic #dimm 1-0-1
 243                                                         device i2c 55 on end
 244                                                 end
 245                                                 chip drivers/generic/generic #dimm 1-1-0
 246                                                         device i2c 56 on end
 247                                                 end
 248                                                 chip drivers/generic/generic #dimm 1-1-1
 249                                                         device i2c 57 on end
 250                                                 end
 251                                         end # SM
 252                                         device pci 1.1 on # SM 1
 253 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 254 #                                                chip drivers/generic/generic #PCIXA Slot1
 255 #                                                        device i2c 50 on end
 256 #                                                end
 257 #                                                chip drivers/generic/generic #PCIXB Slot1
 258 #                                                        device i2c 51 on end
 259 #                                                end
 260 #                                                chip drivers/generic/generic #PCIXB Slot2
 261 #                                                        device i2c 52 on end
 262 #                                                end
 263 #                                                chip drivers/generic/generic #PCI Slot1
 264 #                                                        device i2c 53 on end
 265 #                                                end
 266 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 267 #                                                        device i2c 54 on end
 268 #                                                end
 269 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 270 #                                                        device i2c 55 on end
 271 #                                                end
 272                                                 chip drivers/generic/generic #MAC EEPROM
 273                                                         device i2c 51 on end
 274                                                 end
 275
 276                                         end # SM
 277                                         device pci 2.0 on end # USB 1.1
 278                                         device pci 2.1 on end # USB 2
 279                                         device pci 4.0 on end # IDE
 280                                         device pci 5.0 on end # SATA 0
 281                                         device pci 5.1 on end # SATA 1
 282                                         device pci 5.2 on end # SATA 2
 283                                         device pci 6.0 on  # PCI
 284                                                 chip drivers/pci/onboard
 285                                                         device pci 6.0 on end
 286                                                         register "rom_address" = "0xfff00000" #for 1M
 287 #                                                        register "rom_address" = "0xfff80000" #for 512K
 288                                                 end
 289                                         end
 290                                         device pci 6.1 on end # AZA
 291                                         device pci 8.0 on end # NIC
 292                                         device pci 9.0 on end # NIC
 293                                         device pci a.0 on  # PCI E 5
 294                                                 device pci 0.0 on #nec pci-x
 295                                                 end
 296                                                 device pci 0.1 on #nec pci-x
 297                                                         device pci 4.0 on end #scsi
 298                                                         device pci 4.1 on end #scsi
 299                                                 end
 300                                         end
 301                                         device pci b.0 on end # PCI E 4
 302                                         device pci c.0 on end # PCI E 3
 303                                         device pci d.0 on end # PCI E 2
 304                                         device pci e.0 on end # PCI E 1
 305                                         device pci f.0 on end # PCI E 0
 306                                         register "ide0_enable" = "1"
 307                                         register "sata0_enable" = "1"
 308                                         register "sata1_enable" = "1"
 309                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 310                                         register "mac_eeprom_addr" = "0x51"
 311                                 end
 312                         end #  device pci 18.0
 313                         device pci 18.1 on end
 314                         device pci 18.2 on end
 315                         device pci 18.3 on end
 316                         device pci 18.4 on end
 317                         device pci 19.0 on end
 318                         device pci 19.1 on end
 319                         device pci 19.2 on end
 320                         device pci 19.3 on end
 321                         device pci 19.4 on end
 322                 end # mc0
 323
 324         end # PCI domain
 325
 326 #       chip drivers/generic/debug
 327 #               device pnp 0.0 off end # chip name
 328 #                device pnp 0.1 on end # pci_regs_all
 329 #                device pnp 0.2 off end # mem
 330 #                device pnp 0.3 off end # cpuid
 331 #                device pnp 0.4 on end # smbus_regs_all
 332 #                device pnp 0.5 off end # dual core msr
 333 #                device pnp 0.6 off end # cache size
 334 #                device pnp 0.7 off end # tsc
 335 #                device pnp 0.8 off  end # io
 336 #                device pnp 0.9 on end # io
 337 #       end
 338 end #root_complex