2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <arch/smp/mpspec.h>
24 #include <device/pci.h>
27 #include <cpu/amd/amdk8_sysconf.h>
29 extern unsigned char bus_isa;
30 extern unsigned char bus_mcp55[8]; //1
32 extern unsigned apicid_mcp55;
34 extern unsigned char bus_pcix[3]; // under bus_mcp55_2
36 static void *smp_write_config_table(void *v)
38 struct mp_config_table *mc;
40 unsigned char bus_num;
43 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
45 mptable_init(mc, "H8DMR ", LAPIC_ADDR);
47 smp_write_processors(mc);
53 /* define bus and isa numbers */
54 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
55 smp_write_bus(mc, bus_num, "PCI ");
57 smp_write_bus(mc, bus_isa, "ISA ");
59 /*I/O APICs: APIC ID Version State Address*/
65 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
67 res = find_resource(dev, PCI_BASE_ADDRESS_1);
69 smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
73 pci_write_config32(dev, 0x7c, dword);
76 pci_write_config32(dev, 0x80, dword);
79 pci_write_config32(dev, 0x84, dword);
87 mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
89 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
90 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
92 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
96 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
99 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
105 for(j=7; j>=2; j--) {
106 if(!bus_mcp55[j]) continue;
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17
127 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
128 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
129 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
130 /* There is no extension information... */
132 /* Compute the checksums */
133 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
134 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
135 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
136 mc, smp_next_mpe_entry(mc));
137 return smp_next_mpe_entry(mc);
140 unsigned long write_smp_table(unsigned long addr)
143 v = smp_write_floating_table(addr);
144 return (unsigned long)smp_write_config_table(v);