src/mainboard/supermicro/h8dmr/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  24 include /config/failovercalculation.lb
  25
  26 arch i386 end
  27
  28 ##
  29 ## Build the objects we have code for in this directory.
  30 ##
  31
  32 driver mainboard.o
  33 #needed by irq_tables and mptable and acpi_tables
  34 object get_bus_conf.o
  35
  36 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  37 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  38
  39         if CONFIG_USE_INIT
  40                 makerule ./auto.o
  41                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  42                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  43                 end
  44         else
  45                 makerule ./auto.inc
  46                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  47                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  48                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  49                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  50                 end
  51         end
  52
  53 if CONFIG_USE_FAILOVER_IMAGE
  54 else
  55     if CONFIG_AP_CODE_IN_CAR
  56         makerule ./apc_auto.o
  57                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  58                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  59         end
  60     end
  61 end
  62
  63
  64 ##
  65 ## Build our 16 bit and 32 bit coreboot entry code
  66 ##
  67 if CONFIG_HAVE_FAILOVER_BOOT
  68     if CONFIG_USE_FAILOVER_IMAGE
  69         mainboardinit cpu/x86/16bit/entry16.inc
  70         ldscript /cpu/x86/16bit/entry16.lds
  71     end
  72 else
  73     if CONFIG_USE_FALLBACK_IMAGE
  74         mainboardinit cpu/x86/16bit/entry16.inc
  75         ldscript /cpu/x86/16bit/entry16.lds
  76     end
  77 end
  78
  79 mainboardinit cpu/x86/32bit/entry32.inc
  80
  81         if CONFIG_USE_INIT
  82                 ldscript /cpu/x86/32bit/entry32.lds
  83         end
  84
  85         if CONFIG_USE_INIT
  86                 ldscript /cpu/amd/car/cache_as_ram.lds
  87         end
  88
  89 ##
  90 ## Build our reset vector (This is where coreboot is entered)
  91 ##
  92 if CONFIG_HAVE_FAILOVER_BOOT
  93     if CONFIG_USE_FAILOVER_IMAGE
  94         mainboardinit cpu/x86/16bit/reset16.inc
  95         ldscript /cpu/x86/16bit/reset16.lds
  96     else
  97         mainboardinit cpu/x86/32bit/reset32.inc
  98         ldscript /cpu/x86/32bit/reset32.lds
  99     end
 100 else
 101     if CONFIG_USE_FALLBACK_IMAGE
 102         mainboardinit cpu/x86/16bit/reset16.inc
 103         ldscript /cpu/x86/16bit/reset16.lds
 104     else
 105         mainboardinit cpu/x86/32bit/reset32.inc
 106         ldscript /cpu/x86/32bit/reset32.lds
 107     end
 108 end
 109
 110 ##
 111 ## Include an id string (For safe flashing)
 112 ##
 113 mainboardinit southbridge/nvidia/mcp55/id.inc
 114 ldscript /southbridge/nvidia/mcp55/id.lds
 115
 116 ##
 117 ## ROMSTRAP table for MCP55
 118 ##
 119 if CONFIG_HAVE_FAILOVER_BOOT
 120     if CONFIG_USE_FAILOVER_IMAGE
 121         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 122         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 123     end
 124 else
 125     if CONFIG_USE_FALLBACK_IMAGE
 126         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 127         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 128     end
 129 end
 130
 131         ##
 132         ## Setup Cache-As-Ram
 133         ##
 134         mainboardinit cpu/amd/car/cache_as_ram.inc
 135
 136 ###
 137 ### This is the early phase of coreboot startup
 138 ### Things are delicate and we test to see if we should
 139 ### failover to another image.
 140 ###
 141 if CONFIG_HAVE_FAILOVER_BOOT
 142     if CONFIG_USE_FAILOVER_IMAGE
 143                 ldscript /arch/i386/lib/failover_failover.lds
 144     end
 145 else
 146     if CONFIG_USE_FALLBACK_IMAGE
 147                 ldscript /arch/i386/lib/failover.lds
 148     end
 149 end
 150
 151 ##
 152 ## Setup RAM
 153 ##
 154         if CONFIG_USE_INIT
 155                 initobject auto.o
 156         else
 157                 mainboardinit ./auto.inc
 158         end
 159
 160 ##
 161 ## Include the secondary Configuration files
 162 ##
 163 config chip.h
 164
 165 chip northbridge/amd/amdk8/root_complex
 166         device apic_cluster 0 on
 167                 chip cpu/amd/socket_F
 168                         device apic 0 on end
 169                 end
 170         end
 171         device pci_domain 0 on
 172                 chip northbridge/amd/amdk8 #mc0
 173                         device pci 18.0 on end
 174                         device pci 18.0 on end
 175                         device pci 18.0 on
 176                                 #  devices on link 0, link 0 == LDT 0
 177                                 chip southbridge/nvidia/mcp55
 178                                         device pci 0.0 on end   # HT
 179                                         device pci 1.0 on # LPC
 180                                                 chip superio/winbond/w83627hf
 181                                                         device pnp 2e.0 off #  Floppy
 182                                                                 io 0x60 = 0x3f0
 183                                                                 irq 0x70 = 6
 184                                                                 drq 0x74 = 2
 185                                                         end
 186                                                         device pnp 2e.1 off #  Parallel Port
 187                                                                 io 0x60 = 0x378
 188                                                                 irq 0x70 = 7
 189                                                         end
 190                                                         device pnp 2e.2 on #  Com1
 191                                                                 io 0x60 = 0x3f8
 192                                                                 irq 0x70 = 4
 193                                                         end
 194                                                         device pnp 2e.3 off #  Com2
 195                                                                 io 0x60 = 0x2f8
 196                                                                 irq 0x70 = 3
 197                                                         end
 198                                                         device pnp 2e.5 on #  Keyboard
 199                                                                 io 0x60 = 0x60
 200                                                                 io 0x62 = 0x64
 201                                                                 irq 0x70 = 1
 202                                                                 irq 0x72 = 12
 203                                                         end
 204                                                         device pnp 2e.6 off  # SFI
 205                                                                 io 0x62 = 0x100
 206                                                         end
 207                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 208                                                                 io 0x60 = 0x220
 209                                                                 io 0x62 = 0x300
 210                                                                 irq 0x70 = 9
 211                                                         end
 212                                                         device pnp 2e.8 off end #  WDTO_PLED
 213                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 214                                                         device pnp 2e.a off end #  ACPI
 215                                                         device pnp 2e.b on #  HW Monitor
 216                                                                 io 0x60 = 0x290
 217                                                                 irq 0x70 = 5
 218                                                         end
 219                                                 end
 220                                         end
 221                                         device pci 1.1 on # SM 0
 222                                                 chip drivers/generic/generic #dimm 0-0-0
 223                                                         device i2c 50 on end
 224                                                 end
 225                                                 chip drivers/generic/generic #dimm 0-0-1
 226                                                         device i2c 51 on end
 227                                                 end
 228                                                 chip drivers/generic/generic #dimm 0-1-0
 229                                                         device i2c 52 on end
 230                                                 end
 231                                                 chip drivers/generic/generic #dimm 0-1-1
 232                                                         device i2c 53 on end
 233                                                 end
 234                                                 chip drivers/generic/generic #dimm 1-0-0
 235                                                         device i2c 54 on end
 236                                                 end
 237                                                 chip drivers/generic/generic #dimm 1-0-1
 238                                                         device i2c 55 on end
 239                                                 end
 240                                                 chip drivers/generic/generic #dimm 1-1-0
 241                                                         device i2c 56 on end
 242                                                 end
 243                                                 chip drivers/generic/generic #dimm 1-1-1
 244                                                         device i2c 57 on end
 245                                                 end
 246                                         end # SM
 247                                         device pci 1.1 on # SM 1
 248 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 249 #                                                chip drivers/generic/generic #PCIXA Slot1
 250 #                                                        device i2c 50 on end
 251 #                                                end
 252 #                                                chip drivers/generic/generic #PCIXB Slot1
 253 #                                                        device i2c 51 on end
 254 #                                                end
 255 #                                                chip drivers/generic/generic #PCIXB Slot2
 256 #                                                        device i2c 52 on end
 257 #                                                end
 258 #                                                chip drivers/generic/generic #PCI Slot1
 259 #                                                        device i2c 53 on end
 260 #                                                end
 261 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 262 #                                                        device i2c 54 on end
 263 #                                                end
 264 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 265 #                                                        device i2c 55 on end
 266 #                                                end
 267                                                 chip drivers/generic/generic #MAC EEPROM
 268                                                         device i2c 51 on end
 269                                                 end
 270
 271                                         end # SM
 272                                         device pci 2.0 on end # USB 1.1
 273                                         device pci 2.1 on end # USB 2
 274                                         device pci 4.0 on end # IDE
 275                                         device pci 5.0 on end # SATA 0
 276                                         device pci 5.1 on end # SATA 1
 277                                         device pci 5.2 on end # SATA 2
 278                                         device pci 6.0 on  # PCI
 279                                                 chip drivers/pci/onboard
 280                                                         device pci 6.0 on end
 281                                                         register "rom_address" = "0xfff00000" #for 1M
 282 #                                                        register "rom_address" = "0xfff80000" #for 512K
 283                                                 end
 284                                         end
 285                                         device pci 6.1 on end # AZA
 286                                         device pci 8.0 on end # NIC
 287                                         device pci 9.0 on end # NIC
 288                                         device pci a.0 on  # PCI E 5
 289                                                 device pci 0.0 on #nec pci-x
 290                                                 end
 291                                                 device pci 0.1 on #nec pci-x
 292                                                         device pci 4.0 on end #scsi
 293                                                         device pci 4.1 on end #scsi
 294                                                 end
 295                                         end
 296                                         device pci b.0 on end # PCI E 4
 297                                         device pci c.0 on end # PCI E 3
 298                                         device pci d.0 on end # PCI E 2
 299                                         device pci e.0 on end # PCI E 1
 300                                         device pci f.0 on end # PCI E 0
 301                                         register "ide0_enable" = "1"
 302                                         register "sata0_enable" = "1"
 303                                         register "sata1_enable" = "1"
 304                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 305                                         register "mac_eeprom_addr" = "0x51"
 306                                 end
 307                         end #  device pci 18.0
 308                         device pci 18.1 on end
 309                         device pci 18.2 on end
 310                         device pci 18.3 on end
 311                 end # mc0
 312
 313         end # PCI domain
 314
 315 #       chip drivers/generic/debug
 316 #               device pnp 0.0 off end # chip name
 317 #                device pnp 0.1 on end # pci_regs_all
 318 #                device pnp 0.2 off end # mem
 319 #                device pnp 0.3 off end # cpuid
 320 #                device pnp 0.4 on end # smbus_regs_all
 321 #                device pnp 0.5 off end # dual core msr
 322 #                device pnp 0.6 off end # cache size
 323 #                device pnp 0.7 off end # tsc
 324 #                device pnp 0.8 off  end # io
 325 #                device pnp 0.9 on end # io
 326 #       end
 327 end #root_complex