2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 ## Compute the location and size of where this firmware image
24 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
27 default ROM_SECTION_SIZE = FAILOVER_SIZE
28 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
31 default ROM_SECTION_SIZE = FALLBACK_SIZE
32 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
34 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
35 default ROM_SECTION_OFFSET = 0
40 ## Compute the start location and size size of
41 ## The linuxBIOS bootloader.
43 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
47 ## Compute where this copy of linuxBIOS will start in the boot rom
49 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
52 ## Compute a range of ROM that can cached to speed up linuxBIOS,
55 ## XIP_ROM_SIZE must be a power of 2.
56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
58 default XIP_ROM_SIZE=65536
61 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
64 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
66 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
73 ## Build the objects we have code for in this directory.
77 #needed by irq_tables and mptable and acpi_tables
80 if HAVE_MP_TABLE object mptable.o end
81 if HAVE_PIRQ_TABLE object irq_tables.o end
87 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
88 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
92 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
93 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
94 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
95 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
101 if USE_FAILOVER_IMAGE
103 if CONFIG_AP_CODE_IN_CAR
104 makerule ./apc_auto.o
105 depends "$(MAINBOARD)/apc_auto.c option_table.h"
106 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
108 ldscript /arch/i386/init/ldscript_apc.lb
114 ## Build our 16 bit and 32 bit linuxBIOS entry code
116 if HAVE_FAILOVER_BOOT
117 if USE_FAILOVER_IMAGE
118 mainboardinit cpu/x86/16bit/entry16.inc
119 ldscript /cpu/x86/16bit/entry16.lds
122 if USE_FALLBACK_IMAGE
123 mainboardinit cpu/x86/16bit/entry16.inc
124 ldscript /cpu/x86/16bit/entry16.lds
128 mainboardinit cpu/x86/32bit/entry32.inc
132 ldscript /cpu/x86/32bit/entry32.lds
136 ldscript /cpu/amd/car/cache_as_ram.lds
142 ## Build our reset vector (This is where linuxBIOS is entered)
144 if HAVE_FAILOVER_BOOT
145 if USE_FAILOVER_IMAGE
146 mainboardinit cpu/x86/16bit/reset16.inc
147 ldscript /cpu/x86/16bit/reset16.lds
149 mainboardinit cpu/x86/32bit/reset32.inc
150 ldscript /cpu/x86/32bit/reset32.lds
153 if USE_FALLBACK_IMAGE
154 mainboardinit cpu/x86/16bit/reset16.inc
155 ldscript /cpu/x86/16bit/reset16.lds
157 mainboardinit cpu/x86/32bit/reset32.inc
158 ldscript /cpu/x86/32bit/reset32.lds
163 ## Include an id string (For safe flashing)
165 mainboardinit southbridge/nvidia/mcp55/id.inc
166 ldscript /southbridge/nvidia/mcp55/id.lds
169 ## ROMSTRAP table for MCP55
171 if HAVE_FAILOVER_BOOT
172 if USE_FAILOVER_IMAGE
173 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
174 ldscript /southbridge/nvidia/mcp55/romstrap.lds
177 if USE_FALLBACK_IMAGE
178 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
179 ldscript /southbridge/nvidia/mcp55/romstrap.lds
185 ## Setup Cache-As-Ram
187 mainboardinit cpu/amd/car/cache_as_ram.inc
191 ### This is the early phase of linuxBIOS startup
192 ### Things are delicate and we test to see if we should
193 ### failover to another image.
195 if HAVE_FAILOVER_BOOT
196 if USE_FAILOVER_IMAGE
198 ldscript /arch/i386/lib/failover_failover.lds
202 if USE_FALLBACK_IMAGE
204 ldscript /arch/i386/lib/failover.lds
217 mainboardinit ./auto.inc
222 ## Include the secondary Configuration files
228 chip northbridge/amd/amdk8/root_complex
229 device apic_cluster 0 on
230 chip cpu/amd/socket_F
234 device pci_domain 0 on
235 chip northbridge/amd/amdk8 #mc0
236 device pci 18.0 on end
237 device pci 18.0 on end
239 # devices on link 0, link 0 == LDT 0
240 chip southbridge/nvidia/mcp55
241 device pci 0.0 on end # HT
242 device pci 1.0 on # LPC
243 chip superio/winbond/w83627hf
244 device pnp 2e.0 off # Floppy
249 device pnp 2e.1 off # Parallel Port
253 device pnp 2e.2 on # Com1
257 device pnp 2e.3 off # Com2
261 device pnp 2e.5 on # Keyboard
267 device pnp 2e.6 off # SFI
270 device pnp 2e.7 off # GPIO_GAME_MIDI
275 device pnp 2e.8 off end # WDTO_PLED
276 device pnp 2e.9 off end # GPIO_SUSLED
277 device pnp 2e.a off end # ACPI
278 device pnp 2e.b on # HW Monitor
284 device pci 1.1 on # SM 0
285 chip drivers/generic/generic #dimm 0-0-0
288 chip drivers/generic/generic #dimm 0-0-1
291 chip drivers/generic/generic #dimm 0-1-0
294 chip drivers/generic/generic #dimm 0-1-1
297 chip drivers/generic/generic #dimm 1-0-0
300 chip drivers/generic/generic #dimm 1-0-1
303 chip drivers/generic/generic #dimm 1-1-0
306 chip drivers/generic/generic #dimm 1-1-1
310 device pci 1.1 on # SM 1
311 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
312 # chip drivers/generic/generic #PCIXA Slot1
313 # device i2c 50 on end
315 # chip drivers/generic/generic #PCIXB Slot1
316 # device i2c 51 on end
318 # chip drivers/generic/generic #PCIXB Slot2
319 # device i2c 52 on end
321 # chip drivers/generic/generic #PCI Slot1
322 # device i2c 53 on end
324 # chip drivers/generic/generic #Master MCP55 PCI-E
325 # device i2c 54 on end
327 # chip drivers/generic/generic #Slave MCP55 PCI-E
328 # device i2c 55 on end
330 chip drivers/generic/generic #MAC EEPROM
335 device pci 2.0 on end # USB 1.1
336 device pci 2.1 on end # USB 2
337 device pci 4.0 on end # IDE
338 device pci 5.0 on end # SATA 0
339 device pci 5.1 on end # SATA 1
340 device pci 5.2 on end # SATA 2
341 device pci 6.0 on # PCI
342 chip drivers/pci/onboard
343 device pci 6.0 on end
344 register "rom_address" = "0xfff00000" #for 1M
345 # register "rom_address" = "0xfff80000" #for 512K
348 device pci 6.1 on end # AZA
349 device pci 8.0 on end # NIC
350 device pci 9.0 on end # NIC
351 device pci a.0 on # PCI E 5
352 device pci 0.0 on #nec pci-x
354 device pci 0.1 on #nec pci-x
355 device pci 4.0 on end #scsi
356 device pci 4.1 on end #scsi
359 device pci b.0 on end # PCI E 4
360 device pci c.0 on end # PCI E 3
361 device pci d.0 on end # PCI E 2
362 device pci e.0 on end # PCI E 1
363 device pci f.0 on end # PCI E 0
364 register "ide0_enable" = "1"
365 register "sata0_enable" = "1"
366 register "sata1_enable" = "1"
367 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
368 register "mac_eeprom_addr" = "0x51"
370 end # device pci 18.0
371 device pci 18.1 on end
372 device pci 18.2 on end
373 device pci 18.3 on end
378 # chip drivers/generic/debug
379 # device pnp 0.0 off end # chip name
380 # device pnp 0.1 on end # pci_regs_all
381 # device pnp 0.2 off end # mem
382 # device pnp 0.3 off end # cpuid
383 # device pnp 0.4 on end # smbus_regs_all
384 # device pnp 0.5 off end # dual core msr
385 # device pnp 0.6 off end # cache size
386 # device pnp 0.7 off end # tsc
387 # device pnp 0.8 off end # io
388 # device pnp 0.9 on end # io