2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 static void setup_mb_resource_map(void)
24 static const unsigned int register_values[] = {
25 /* Careful set limit registers before base registers which contain the enables */
26 /* DRAM Limit i Registers
35 * [ 2: 0] Destination Node ID
45 * [10: 8] Interleave select
46 * specifies the values of A[14:12] to use with interleave enable.
48 * [31:16] DRAM Limit Address i Bits 39-24
49 * This field defines the upper address bits of a 40 bit address
50 * that define the end of the DRAM region.
52 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
53 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
54 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
55 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
56 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
57 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
58 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
59 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
61 /* DRAM Base i Registers
73 * [ 1: 1] Write Enable
77 * [10: 8] Interleave Enable
79 * 001 = Interleave on A[12] (2 nodes)
81 * 011 = Interleave on A[12] and A[14] (4 nodes)
85 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
87 * [13:16] DRAM Base Address i Bits 39-24
88 * This field defines the upper address bits of a 40-bit address
89 * that define the start of the DRAM region.
91 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
92 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
93 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
94 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
95 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
96 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
97 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
98 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
100 /* Memory-Mapped I/O Limit i Registers
109 * [ 2: 0] Destination Node ID
119 * [ 5: 4] Destination Link ID
126 * 0 = CPU writes may be posted
127 * 1 = CPU writes must be non-posted
128 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
129 * This field defines the upp adddress bits of a 40-bit address that
130 * defines the end of a memory-mapped I/O region n
132 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
133 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
134 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
135 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
136 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
137 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
138 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
139 // PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
141 /* Memory-Mapped I/O Base i Registers
150 * [ 0: 0] Read Enable
153 * [ 1: 1] Write Enable
154 * 0 = Writes disabled
156 * [ 2: 2] Cpu Disable
157 * 0 = Cpu can use this I/O range
158 * 1 = Cpu requests do not use this I/O range
160 * 0 = base/limit registers i are read/write
161 * 1 = base/limit registers i are read-only
163 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
164 * This field defines the upper address bits of a 40bit address
165 * that defines the start of memory-mapped I/O region i
167 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
168 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
169 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
170 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
171 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
172 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
173 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
174 // PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
176 /* PCI I/O Limit i Registers
181 * [ 2: 0] Destination Node ID
191 * [ 5: 4] Destination Link ID
197 * [24:12] PCI I/O Limit Address i
198 * This field defines the end of PCI I/O region n
201 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
202 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, // need to talk to ANALOG of second CK804 to release PCI E reset
203 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
204 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
206 /* PCI I/O Base i Registers
211 * [ 0: 0] Read Enable
214 * [ 1: 1] Write Enable
215 * 0 = Writes Disabled
219 * 0 = VGA matches Disabled
220 * 1 = matches all address < 64K and where A[9:0] is in the
221 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
223 * 0 = ISA matches Disabled
224 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
225 * from matching agains this base/limit pair
227 * [24:12] PCI I/O Base i
228 * This field defines the start of PCI I/O region n
231 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
232 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
233 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
234 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
236 /* Config Base and Limit i Registers
241 * [ 0: 0] Read Enable
244 * [ 1: 1] Write Enable
245 * 0 = Writes Disabled
247 * [ 2: 2] Device Number Compare Enable
248 * 0 = The ranges are based on bus number
249 * 1 = The ranges are ranges of devices on bus 0
251 * [ 6: 4] Destination Node
261 * [ 9: 8] Destination Link
267 * [23:16] Bus Number Base i
268 * This field defines the lowest bus number in configuration region i
269 * [31:24] Bus Number Limit i
270 * This field defines the highest bus number in configuration region i
272 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */
273 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
274 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
275 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
280 max = ARRAY_SIZE(register_values);
281 setup_resource_map(register_values, max);