src/mainboard/supermicro/h8dme/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## This program is free software; you can redistribute it and/or modify
   5 ## it under the terms of the GNU General Public License as published by
   6 ## the Free Software Foundation; either version 2 of the License, or
   7 ## (at your option) any later version.
   8 ##
   9 ## This program is distributed in the hope that it will be useful,
  10 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 ## GNU General Public License for more details.
  13 ##
  14 ## You should have received a copy of the GNU General Public License
  15 ## along with this program; if not, write to the Free Software
  16 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  17 ##
  18
  19 include /config/failovercalculation.lb
  20
  21 arch i386 end
  22
  23 ##
  24 ## Build the objects we have code for in this directory.
  25 ##
  26
  27 driver mainboard.o
  28 #needed by irq_tables and mptable and acpi_tables
  29 object get_bus_conf.o
  30
  31 if HAVE_MP_TABLE object mptable.o end
  32 if HAVE_PIRQ_TABLE object irq_tables.o end
  33 #object reset.o
  34
  35         if CONFIG_USE_INIT
  36                 makerule ./auto.o
  37                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  38                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  39                 end
  40         else
  41                 makerule ./auto.inc
  42                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  43                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  44                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  45                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  46                 end
  47         end
  48
  49 if USE_FAILOVER_IMAGE
  50 else
  51     if CONFIG_AP_CODE_IN_CAR
  52         makerule ./apc_auto.o
  53                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
  54                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
  55         end
  56         ldscript /arch/i386/init/ldscript_apc.lb
  57     end
  58 end
  59
  60
  61 ##
  62 ## Build our 16 bit and 32 bit coreboot entry code
  63 ##
  64 if HAVE_FAILOVER_BOOT
  65     if USE_FAILOVER_IMAGE
  66         mainboardinit cpu/x86/16bit/entry16.inc
  67         ldscript /cpu/x86/16bit/entry16.lds
  68     end
  69 else
  70     if USE_FALLBACK_IMAGE
  71         mainboardinit cpu/x86/16bit/entry16.inc
  72         ldscript /cpu/x86/16bit/entry16.lds
  73     end
  74 end
  75
  76 mainboardinit cpu/x86/32bit/entry32.inc
  77
  78         if CONFIG_USE_INIT
  79                 ldscript /cpu/x86/32bit/entry32.lds
  80         end
  81
  82         if CONFIG_USE_INIT
  83                 ldscript /cpu/amd/car/cache_as_ram.lds
  84         end
  85
  86 ##
  87 ## Build our reset vector (This is where coreboot is entered)
  88 ##
  89 if HAVE_FAILOVER_BOOT
  90     if USE_FAILOVER_IMAGE
  91         mainboardinit cpu/x86/16bit/reset16.inc
  92         ldscript /cpu/x86/16bit/reset16.lds
  93     else
  94         mainboardinit cpu/x86/32bit/reset32.inc
  95         ldscript /cpu/x86/32bit/reset32.lds
  96     end
  97 else
  98     if USE_FALLBACK_IMAGE
  99         mainboardinit cpu/x86/16bit/reset16.inc
 100         ldscript /cpu/x86/16bit/reset16.lds
 101     else
 102         mainboardinit cpu/x86/32bit/reset32.inc
 103         ldscript /cpu/x86/32bit/reset32.lds
 104     end
 105 end
 106
 107 ##
 108 ## Include an id string (For safe flashing)
 109 ##
 110 mainboardinit southbridge/nvidia/mcp55/id.inc
 111 ldscript /southbridge/nvidia/mcp55/id.lds
 112
 113 ##
 114 ## ROMSTRAP table for MCP55
 115 ##
 116 if HAVE_FAILOVER_BOOT
 117     if USE_FAILOVER_IMAGE
 118         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 119         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 120     end
 121 else
 122     if USE_FALLBACK_IMAGE
 123         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 124         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 125     end
 126 end
 127
 128         ##
 129         ## Setup Cache-As-Ram
 130         ##
 131         mainboardinit cpu/amd/car/cache_as_ram.inc
 132
 133 ###
 134 ### This is the early phase of coreboot startup
 135 ### Things are delicate and we test to see if we should
 136 ### failover to another image.
 137 ###
 138 if HAVE_FAILOVER_BOOT
 139     if USE_FAILOVER_IMAGE
 140                 ldscript /arch/i386/lib/failover_failover.lds
 141     end
 142 else
 143     if USE_FALLBACK_IMAGE
 144                 ldscript /arch/i386/lib/failover.lds
 145     end
 146 end
 147
 148 ##
 149 ## Setup RAM
 150 ##
 151         if CONFIG_USE_INIT
 152                 initobject auto.o
 153         else
 154                 mainboardinit ./auto.inc
 155         end
 156
 157 ##
 158 ## Include the secondary Configuration files
 159 ##
 160 config chip.h
 161
 162 chip northbridge/amd/amdk8/root_complex
 163         device apic_cluster 0 on
 164                 chip cpu/amd/socket_F
 165                         device apic 0 on end
 166                 end
 167         end
 168         device pci_domain 0 on
 169                 chip northbridge/amd/amdk8 #mc0
 170                         device pci 18.0 on end
 171                         device pci 18.0 on end
 172                         device pci 18.0 on
 173                                 #  devices on link 0, link 0 == LDT 0
 174                                 chip southbridge/nvidia/mcp55
 175                                         device pci 0.0 on end   # HT
 176                                         device pci 1.0 on # LPC
 177                                                 chip superio/winbond/w83627hf
 178                                                         device pnp 2e.0 off #  Floppy
 179                                                                 io 0x60 = 0x3f0
 180                                                                 irq 0x70 = 6
 181                                                                 drq 0x74 = 2
 182                                                         end
 183                                                         device pnp 2e.1 off #  Parallel Port
 184                                                                 io 0x60 = 0x378
 185                                                                 irq 0x70 = 7
 186                                                         end
 187                                                         device pnp 2e.2 on #  Com1
 188                                                                 io 0x60 = 0x3f8
 189                                                                 irq 0x70 = 4
 190                                                         end
 191                                                         device pnp 2e.3 off #  Com2
 192                                                                 io 0x60 = 0x2f8
 193                                                                 irq 0x70 = 3
 194                                                         end
 195                                                         device pnp 2e.5 on #  Keyboard
 196                                                                 io 0x60 = 0x60
 197                                                                 io 0x62 = 0x64
 198                                                                 irq 0x70 = 1
 199                                                                 irq 0x72 = 12
 200                                                         end
 201                                                         device pnp 2e.6 off  # SFI
 202                                                                 io 0x62 = 0x100
 203                                                         end
 204                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 205                                                                 io 0x60 = 0x220
 206                                                                 io 0x62 = 0x300
 207                                                                 irq 0x70 = 9
 208                                                         end
 209                                                         device pnp 2e.8 off end #  WDTO_PLED
 210                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 211                                                         device pnp 2e.a off end #  ACPI
 212                                                         device pnp 2e.b on #  HW Monitor
 213                                                                 io 0x60 = 0x290
 214                                                                 irq 0x70 = 5
 215                                                         end
 216                                                 end
 217                                         end
 218                                         device pci 1.1 on # SM 0
 219                                                 chip drivers/i2c/i2cmux2
 220                                                         device i2c 48 off end
 221                                                         device i2c 49 off end
 222                                                 end
 223                                         end # SM
 224                                         device pci 1.1 on # SM 1
 225 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 226 #                                                chip drivers/generic/generic #PCIXA Slot1
 227 #                                                        device i2c 50 on end
 228 #                                                end
 229 #                                                chip drivers/generic/generic #PCIXB Slot1
 230 #                                                        device i2c 51 on end
 231 #                                                end
 232 #                                                chip drivers/generic/generic #PCIXB Slot2
 233 #                                                        device i2c 52 on end
 234 #                                                end
 235 #                                                chip drivers/generic/generic #PCI Slot1
 236 #                                                        device i2c 53 on end
 237 #                                                end
 238 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 239 #                                                        device i2c 54 on end
 240 #                                                end
 241 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 242 #                                                        device i2c 55 on end
 243 #                                                end
 244                                                 chip drivers/generic/generic #MAC EEPROM
 245                                                         device i2c 51 on end
 246                                                 end
 247
 248                                         end # SM
 249                                         device pci 2.0 on end # USB 1.1
 250                                         device pci 2.1 on end # USB 2
 251                                         device pci 4.0 on end # IDE
 252                                         device pci 5.0 on end # SATA 0
 253                                         device pci 5.1 on end # SATA 1
 254                                         device pci 5.2 on end # SATA 2
 255                                         device pci 6.0 on  # PCI
 256                                                 chip drivers/pci/onboard
 257                                                         device pci 6.0 on end
 258                                                         register "rom_address" = "0xfff00000" #for 1M
 259 #                                                        register "rom_address" = "0xfff80000" #for 512K
 260                                                 end
 261                                         end
 262                                         device pci 6.1 on end # AZA
 263                                         device pci 8.0 on end # NIC
 264                                         device pci 9.0 on end # NIC
 265                                         device pci a.0 on  # PCI E 5
 266                                                 device pci 0.0 on #nec pci-x
 267                                                 end
 268                                                 device pci 0.1 on #nec pci-x
 269                                                         device pci 4.0 on end #scsi
 270                                                         device pci 4.1 on end #scsi
 271                                                 end
 272                                         end
 273                                         device pci b.0 on end # PCI E 4
 274                                         device pci c.0 on end # PCI E 3
 275                                         device pci d.0 on end # PCI E 2
 276                                         device pci e.0 on end # PCI E 1
 277                                         device pci f.0 on end # PCI E 0
 278                                         register "ide0_enable" = "1"
 279                                         register "sata0_enable" = "1"
 280                                         register "sata1_enable" = "1"
 281                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 282                                         register "mac_eeprom_addr" = "0x51"
 283                                 end
 284                         end #  device pci 18.0
 285                         device pci 18.1 on end
 286                         device pci 18.2 on end
 287                         device pci 18.3 on end
 288                 end # mc0
 289
 290         end # PCI domain
 291
 292 #       chip drivers/generic/debug
 293 #               device pnp 0.0 off end # chip name
 294 #                device pnp 0.1 on end # pci_regs_all
 295 #                device pnp 0.2 off end # mem
 296 #                device pnp 0.3 off end # cpuid
 297 #                device pnp 0.4 on end # smbus_regs_all
 298 #                device pnp 0.5 off end # dual core msr
 299 #                device pnp 0.6 off end # cache size
 300 #                device pnp 0.7 off end # tsc
 301 #                device pnp 0.8 off  end # io
 302 #                device pnp 0.9 on end # io
 303 #       end
 304 end #root_complex