src/mainboard/supermicro/h8dme/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## This program is free software; you can redistribute it and/or modify
   5 ## it under the terms of the GNU General Public License as published by
   6 ## the Free Software Foundation; either version 2 of the License, or
   7 ## (at your option) any later version.
   8 ##
   9 ## This program is distributed in the hope that it will be useful,
  10 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 ## GNU General Public License for more details.
  13 ##
  14 ## You should have received a copy of the GNU General Public License
  15 ## along with this program; if not, write to the Free Software
  16 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  17 ##
  18
  19 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  20 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  21 include /config/failovercalculation.lb
  22
  23 arch i386 end
  24
  25 ##
  26 ## Build the objects we have code for in this directory.
  27 ##
  28
  29 driver mainboard.o
  30 #needed by irq_tables and mptable and acpi_tables
  31 object get_bus_conf.o
  32
  33 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  34 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  35 #object reset.o
  36
  37         if CONFIG_USE_INIT
  38                 makerule ./auto.o
  39                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  40                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  41                 end
  42         else
  43                 makerule ./auto.inc
  44                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  45                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  46                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  47                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  48                 end
  49         end
  50
  51 if CONFIG_USE_FAILOVER_IMAGE
  52 else
  53     if CONFIG_AP_CODE_IN_CAR
  54         makerule ./apc_auto.o
  55                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  56                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  57         end
  58         ldscript /arch/i386/init/ldscript_apc.lb
  59     end
  60 end
  61
  62
  63 ##
  64 ## Build our 16 bit and 32 bit coreboot entry code
  65 ##
  66 if CONFIG_HAVE_FAILOVER_BOOT
  67     if CONFIG_USE_FAILOVER_IMAGE
  68         mainboardinit cpu/x86/16bit/entry16.inc
  69         ldscript /cpu/x86/16bit/entry16.lds
  70     end
  71 else
  72     if CONFIG_USE_FALLBACK_IMAGE
  73         mainboardinit cpu/x86/16bit/entry16.inc
  74         ldscript /cpu/x86/16bit/entry16.lds
  75     end
  76 end
  77
  78 mainboardinit cpu/x86/32bit/entry32.inc
  79
  80         if CONFIG_USE_INIT
  81                 ldscript /cpu/x86/32bit/entry32.lds
  82         end
  83
  84         if CONFIG_USE_INIT
  85                 ldscript /cpu/amd/car/cache_as_ram.lds
  86         end
  87
  88 ##
  89 ## Build our reset vector (This is where coreboot is entered)
  90 ##
  91 if CONFIG_HAVE_FAILOVER_BOOT
  92     if CONFIG_USE_FAILOVER_IMAGE
  93         mainboardinit cpu/x86/16bit/reset16.inc
  94         ldscript /cpu/x86/16bit/reset16.lds
  95     else
  96         mainboardinit cpu/x86/32bit/reset32.inc
  97         ldscript /cpu/x86/32bit/reset32.lds
  98     end
  99 else
 100     if CONFIG_USE_FALLBACK_IMAGE
 101         mainboardinit cpu/x86/16bit/reset16.inc
 102         ldscript /cpu/x86/16bit/reset16.lds
 103     else
 104         mainboardinit cpu/x86/32bit/reset32.inc
 105         ldscript /cpu/x86/32bit/reset32.lds
 106     end
 107 end
 108
 109 ##
 110 ## Include an id string (For safe flashing)
 111 ##
 112 mainboardinit southbridge/nvidia/mcp55/id.inc
 113 ldscript /southbridge/nvidia/mcp55/id.lds
 114
 115 ##
 116 ## ROMSTRAP table for MCP55
 117 ##
 118 if CONFIG_HAVE_FAILOVER_BOOT
 119     if CONFIG_USE_FAILOVER_IMAGE
 120         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 121         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 122     end
 123 else
 124     if CONFIG_USE_FALLBACK_IMAGE
 125         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 126         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 127     end
 128 end
 129
 130         ##
 131         ## Setup Cache-As-Ram
 132         ##
 133         mainboardinit cpu/amd/car/cache_as_ram.inc
 134
 135 ###
 136 ### This is the early phase of coreboot startup
 137 ### Things are delicate and we test to see if we should
 138 ### failover to another image.
 139 ###
 140 if CONFIG_HAVE_FAILOVER_BOOT
 141     if CONFIG_USE_FAILOVER_IMAGE
 142                 ldscript /arch/i386/lib/failover_failover.lds
 143     end
 144 else
 145     if CONFIG_USE_FALLBACK_IMAGE
 146                 ldscript /arch/i386/lib/failover.lds
 147     end
 148 end
 149
 150 ##
 151 ## Setup RAM
 152 ##
 153         if CONFIG_USE_INIT
 154                 initobject auto.o
 155         else
 156                 mainboardinit ./auto.inc
 157         end
 158
 159 ##
 160 ## Include the secondary Configuration files
 161 ##
 162 config chip.h
 163
 164 chip northbridge/amd/amdk8/root_complex
 165         device apic_cluster 0 on
 166                 chip cpu/amd/socket_F
 167                         device apic 0 on end
 168                 end
 169         end
 170         device pci_domain 0 on
 171                 chip northbridge/amd/amdk8 #mc0
 172                         device pci 18.0 on end
 173                         device pci 18.0 on end
 174                         device pci 18.0 on
 175                                 #  devices on link 0, link 0 == LDT 0
 176                                 chip southbridge/nvidia/mcp55
 177                                         device pci 0.0 on end   # HT
 178                                         device pci 1.0 on # LPC
 179                                                 chip superio/winbond/w83627hf
 180                                                         device pnp 2e.0 off #  Floppy
 181                                                                 io 0x60 = 0x3f0
 182                                                                 irq 0x70 = 6
 183                                                                 drq 0x74 = 2
 184                                                         end
 185                                                         device pnp 2e.1 off #  Parallel Port
 186                                                                 io 0x60 = 0x378
 187                                                                 irq 0x70 = 7
 188                                                         end
 189                                                         device pnp 2e.2 on #  Com1
 190                                                                 io 0x60 = 0x3f8
 191                                                                 irq 0x70 = 4
 192                                                         end
 193                                                         device pnp 2e.3 off #  Com2
 194                                                                 io 0x60 = 0x2f8
 195                                                                 irq 0x70 = 3
 196                                                         end
 197                                                         device pnp 2e.5 on #  Keyboard
 198                                                                 io 0x60 = 0x60
 199                                                                 io 0x62 = 0x64
 200                                                                 irq 0x70 = 1
 201                                                                 irq 0x72 = 12
 202                                                         end
 203                                                         device pnp 2e.6 off  # SFI
 204                                                                 io 0x62 = 0x100
 205                                                         end
 206                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 207                                                                 io 0x60 = 0x220
 208                                                                 io 0x62 = 0x300
 209                                                                 irq 0x70 = 9
 210                                                         end
 211                                                         device pnp 2e.8 off end #  WDTO_PLED
 212                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 213                                                         device pnp 2e.a off end #  ACPI
 214                                                         device pnp 2e.b on #  HW Monitor
 215                                                                 io 0x60 = 0x290
 216                                                                 irq 0x70 = 5
 217                                                         end
 218                                                 end
 219                                         end
 220                                         device pci 1.1 on # SM 0
 221                                                 chip drivers/i2c/i2cmux2
 222                                                         device i2c 48 off end
 223                                                         device i2c 49 off end
 224                                                 end
 225                                         end # SM
 226                                         device pci 1.1 on # SM 1
 227 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 228 #                                                chip drivers/generic/generic #PCIXA Slot1
 229 #                                                        device i2c 50 on end
 230 #                                                end
 231 #                                                chip drivers/generic/generic #PCIXB Slot1
 232 #                                                        device i2c 51 on end
 233 #                                                end
 234 #                                                chip drivers/generic/generic #PCIXB Slot2
 235 #                                                        device i2c 52 on end
 236 #                                                end
 237 #                                                chip drivers/generic/generic #PCI Slot1
 238 #                                                        device i2c 53 on end
 239 #                                                end
 240 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 241 #                                                        device i2c 54 on end
 242 #                                                end
 243 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 244 #                                                        device i2c 55 on end
 245 #                                                end
 246                                                 chip drivers/generic/generic #MAC EEPROM
 247                                                         device i2c 51 on end
 248                                                 end
 249
 250                                         end # SM
 251                                         device pci 2.0 on end # USB 1.1
 252                                         device pci 2.1 on end # USB 2
 253                                         device pci 4.0 on end # IDE
 254                                         device pci 5.0 on end # SATA 0
 255                                         device pci 5.1 on end # SATA 1
 256                                         device pci 5.2 on end # SATA 2
 257                                         device pci 6.0 on  # PCI
 258                                                 chip drivers/pci/onboard
 259                                                         device pci 6.0 on end
 260                                                         register "rom_address" = "0xfff00000" #for 1M
 261 #                                                        register "rom_address" = "0xfff80000" #for 512K
 262                                                 end
 263                                         end
 264                                         device pci 6.1 on end # AZA
 265                                         device pci 8.0 on end # NIC
 266                                         device pci 9.0 on end # NIC
 267                                         device pci a.0 on  # PCI E 5
 268                                                 device pci 0.0 on #nec pci-x
 269                                                 end
 270                                                 device pci 0.1 on #nec pci-x
 271                                                         device pci 4.0 on end #scsi
 272                                                         device pci 4.1 on end #scsi
 273                                                 end
 274                                         end
 275                                         device pci b.0 on end # PCI E 4
 276                                         device pci c.0 on end # PCI E 3
 277                                         device pci d.0 on end # PCI E 2
 278                                         device pci e.0 on end # PCI E 1
 279                                         device pci f.0 on end # PCI E 0
 280                                         register "ide0_enable" = "1"
 281                                         register "sata0_enable" = "1"
 282                                         register "sata1_enable" = "1"
 283                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 284                                         register "mac_eeprom_addr" = "0x51"
 285                                 end
 286                         end #  device pci 18.0
 287                         device pci 18.1 on end
 288                         device pci 18.2 on end
 289                         device pci 18.3 on end
 290                 end # mc0
 291
 292         end # PCI domain
 293
 294 #       chip drivers/generic/debug
 295 #               device pnp 0.0 off end # chip name
 296 #                device pnp 0.1 on end # pci_regs_all
 297 #                device pnp 0.2 off end # mem
 298 #                device pnp 0.3 off end # cpuid
 299 #                device pnp 0.4 on end # smbus_regs_all
 300 #                device pnp 0.5 off end # dual core msr
 301 #                device pnp 0.6 off end # cache size
 302 #                device pnp 0.7 off end # tsc
 303 #                device pnp 0.8 off  end # io
 304 #                device pnp 0.9 on end # io
 305 #       end
 306 end #root_complex