src/mainboard/sunw/ultra40/romstage.c

   1 #if CONFIG_LOGICAL_CPUS==1
   2 #define SET_NB_CFG_54 1
   3 #endif
   4
   5
   6 #include <stdint.h>
   7 #include <string.h>
   8 #include <device/pci_def.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14 #include <console/console.h>
  15 #include <lib.h>
  16
  17 #include <cpu/amd/model_fxx_rev.h>
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23
  24 #include "cpu/x86/lapic/boot_cpu.c"
  25 #include "northbridge/amd/amdk8/reset_test.c"
  26 #include "northbridge/amd/amdk8/debug.c"
  27 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  28
  29 #include "cpu/x86/mtrr/earlymtrr.c"
  30 #include "cpu/x86/bist.h"
  31
  32 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  33
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  37
  38 static void memreset(int controllers, const struct mem_controller *ctrl)
  39 {
  40 }
  41
  42 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  43
  44 #define SUPERIO_GPIO_IO_BASE 0x400
  45
  46 #ifdef ENABLE_ONBOARD_SCSI
  47 static void sio_gpio_setup(void)
  48 {
  49         unsigned value;
  50
  51         /*Enable onboard scsi*/
  52         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  53         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  54         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  55 }
  56 #endif
  57
  58 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  59 {
  60         /* nothing to do */
  61 }
  62
  63 static inline int spd_read_byte(unsigned device, unsigned address)
  64 {
  65         return smbus_read_byte(device, address);
  66 }
  67
  68 #include "northbridge/amd/amdk8/raminit.c"
  69 #include "northbridge/amd/amdk8/coherent_ht.c"
  70 #include "lib/generic_sdram.c"
  71
  72  /* tyan does not want the default */
  73 #include "resourcemap.c"
  74
  75 #include "cpu/amd/dualcore/dualcore.c"
  76
  77 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  78
  79 //set GPIO to input mode
  80 #define CK804_MB_SETUP \
  81                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
  82                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
  83                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
  84                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
  85                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
  86                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
  87
  88 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  89
  90
  91
  92 #include "cpu/amd/car/post_cache_as_ram.c"
  93
  94 #include "cpu/amd/model_fxx/init_cpus.c"
  95
  96 #include "northbridge/amd/amdk8/early_ht.c"
  97
  98 static void sio_setup(void)
  99 {
 100         unsigned value;
 101         uint32_t dword;
 102         uint8_t byte;
 103
 104         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 105
 106         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 107         byte |= 0x20;
 108         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 109
 110         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 111         dword |= (1<<29)|(1<<0);
 112         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 113
 114         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 115
 116         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 117         value &= 0xbf;
 118         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 119 }
 120
 121 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 122 {
 123         static const uint16_t spd_addr [] = {
 124                         // Node 0
 125                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 126                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 127                         // Node 1
 128                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 129                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 130         };
 131
 132         int needs_reset;
 133         unsigned bsp_apicid = 0;
 134
 135         struct mem_controller ctrl[8];
 136         unsigned nodes;
 137
 138         if (!cpu_init_detectedx && boot_cpu()) {
 139                 /* Nothing special needs to be done to find bus 0 */
 140                 /* Allow the HT devices to be found */
 141
 142                 enumerate_ht_chain();
 143
 144                 sio_setup();
 145         }
 146
 147         if (bist == 0) {
 148                 bsp_apicid = init_cpus(cpu_init_detectedx);
 149         }
 150
 151         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 152         uart_init();
 153         console_init();
 154
 155         /* Halt if there was a built in self test failure */
 156         report_bist_failure(bist);
 157
 158         setup_ultra40_resource_map();
 159
 160         needs_reset = setup_coherent_ht_domain();
 161
 162         wait_all_core0_started();
 163 #if CONFIG_LOGICAL_CPUS==1
 164         // It is said that we should start core1 after all core0 launched
 165         start_other_cores();
 166         wait_all_other_cores_started(bsp_apicid);
 167 #endif
 168
 169         needs_reset |= ht_setup_chains_x();
 170
 171         needs_reset |= ck804_early_setup_x();
 172
 173         if (needs_reset) {
 174                 print_info("ht reset -\n");
 175                 soft_reset();
 176         }
 177
 178         allow_all_aps_stop(bsp_apicid);
 179
 180         nodes = get_nodes();
 181         //It's the time to set ctrl now;
 182         fill_mem_ctrl(nodes, ctrl, spd_addr);
 183
 184         enable_smbus();
 185
 186         sdram_initialize(nodes, ctrl);
 187
 188         post_cache_as_ram();
 189 }
 190