src/mainboard/sunw/ultra40/resourcemap.c

   1 /*
   2  * needs a different resource map
   3  *
   4  */
   5
   6 static void setup_ultra40_resource_map(void)
   7 {
   8         static const unsigned int register_values[] = {
   9                 /* Careful set limit registers before base registers which contain the enables */
  10                 /* DRAM Limit i Registers
  11                  * F1:0x44 i = 0
  12                  * F1:0x4C i = 1
  13                  * F1:0x54 i = 2
  14                  * F1:0x5C i = 3
  15                  * F1:0x64 i = 4
  16                  * F1:0x6C i = 5
  17                  * F1:0x74 i = 6
  18                  * F1:0x7C i = 7
  19                  * [ 2: 0] Destination Node ID
  20                  *         000 = Node 0
  21                  *         001 = Node 1
  22                  *         010 = Node 2
  23                  *         011 = Node 3
  24                  *         100 = Node 4
  25                  *         101 = Node 5
  26                  *         110 = Node 6
  27                  *         111 = Node 7
  28                  * [ 7: 3] Reserved
  29                  * [10: 8] Interleave select
  30                  *         specifies the values of A[14:12] to use with interleave enable.
  31                  * [15:11] Reserved
  32                  * [31:16] DRAM Limit Address i Bits 39-24
  33                  *         This field defines the upper address bits of a 40 bit  address
  34                  *         that define the end of the DRAM region.
  35                  */
  36                 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
  37                 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
  38                 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
  39                 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
  40                 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
  41                 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
  42                 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
  43                 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
  44
  45                 /* DRAM Base i Registers
  46                  * F1:0x40 i = 0
  47                  * F1:0x48 i = 1
  48                  * F1:0x50 i = 2
  49                  * F1:0x58 i = 3
  50                  * F1:0x60 i = 4
  51                  * F1:0x68 i = 5
  52                  * F1:0x70 i = 6
  53                  * F1:0x78 i = 7
  54                  * [ 0: 0] Read Enable
  55                  *         0 = Reads Disabled
  56                  *         1 = Reads Enabled
  57                  * [ 1: 1] Write Enable
  58                  *         0 = Writes Disabled
  59                  *         1 = Writes Enabled
  60                  * [ 7: 2] Reserved
  61                  * [10: 8] Interleave Enable
  62                  *         000 = No interleave
  63                  *         001 = Interleave on A[12] (2 nodes)
  64                  *         010 = reserved
  65                  *         011 = Interleave on A[12] and A[14] (4 nodes)
  66                  *         100 = reserved
  67                  *         101 = reserved
  68                  *         110 = reserved
  69                  *         111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
  70                  * [15:11] Reserved
  71                  * [13:16] DRAM Base Address i Bits 39-24
  72                  *         This field defines the upper address bits of a 40-bit address
  73                  *         that define the start of the DRAM region.
  74                  */
  75                 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
  76                 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
  77                 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
  78                 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
  79                 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
  80                 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
  81                 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
  82                 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
  83
  84                 /* Memory-Mapped I/O Limit i Registers
  85                  * F1:0x84 i = 0
  86                  * F1:0x8C i = 1
  87                  * F1:0x94 i = 2
  88                  * F1:0x9C i = 3
  89                  * F1:0xA4 i = 4
  90                  * F1:0xAC i = 5
  91                  * F1:0xB4 i = 6
  92                  * F1:0xBC i = 7
  93                  * [ 2: 0] Destination Node ID
  94                  *         000 = Node 0
  95                  *         001 = Node 1
  96                  *         010 = Node 2
  97                  *         011 = Node 3
  98                  *         100 = Node 4
  99                  *         101 = Node 5
 100                  *         110 = Node 6
 101                  *         111 = Node 7
 102                  * [ 3: 3] Reserved
 103                  * [ 5: 4] Destination Link ID
 104                  *         00 = Link 0
 105                  *         01 = Link 1
 106                  *         10 = Link 2
 107                  *         11 = Reserved
 108                  * [ 6: 6] Reserved
 109                  * [ 7: 7] Non-Posted
 110                  *         0 = CPU writes may be posted
 111                  *         1 = CPU writes must be non-posted
 112                  * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
 113                  *         This field defines the upp adddress bits of a 40-bit address that
 114                  *         defines the end of a memory-mapped I/O region n
 115                  */
 116                 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
 117                 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
 118                 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
 119                 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
 120                 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
 121                 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
 122                 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
 123 //              PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
 124
 125                 /* Memory-Mapped I/O Base i Registers
 126                  * F1:0x80 i = 0
 127                  * F1:0x88 i = 1
 128                  * F1:0x90 i = 2
 129                  * F1:0x98 i = 3
 130                  * F1:0xA0 i = 4
 131                  * F1:0xA8 i = 5
 132                  * F1:0xB0 i = 6
 133                  * F1:0xB8 i = 7
 134                  * [ 0: 0] Read Enable
 135                  *         0 = Reads disabled
 136                  *         1 = Reads Enabled
 137                  * [ 1: 1] Write Enable
 138                  *         0 = Writes disabled
 139                  *         1 = Writes Enabled
 140                  * [ 2: 2] Cpu Disable
 141                  *         0 = Cpu can use this I/O range
 142                  *         1 = Cpu requests do not use this I/O range
 143                  * [ 3: 3] Lock
 144                  *         0 = base/limit registers i are read/write
 145                  *         1 = base/limit registers i are read-only
 146                  * [ 7: 4] Reserved
 147                  * [31: 8] Memory-Mapped I/O Base Address i (39-16)
 148                  *         This field defines the upper address bits of a 40bit address
 149                  *         that defines the start of memory-mapped I/O region i
 150                  */
 151                 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
 152                 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
 153                 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
 154                 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
 155                 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
 156                 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
 157                 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
 158 //              PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
 159
 160                 /* PCI I/O Limit i Registers
 161                  * F1:0xC4 i = 0
 162                  * F1:0xCC i = 1
 163                  * F1:0xD4 i = 2
 164                  * F1:0xDC i = 3
 165                  * [ 2: 0] Destination Node ID
 166                  *         000 = Node 0
 167                  *         001 = Node 1
 168                  *         010 = Node 2
 169                  *         011 = Node 3
 170                  *         100 = Node 4
 171                  *         101 = Node 5
 172                  *         110 = Node 6
 173                  *         111 = Node 7
 174                  * [ 3: 3] Reserved
 175                  * [ 5: 4] Destination Link ID
 176                  *         00 = Link 0
 177                  *         01 = Link 1
 178                  *         10 = Link 2
 179                  *         11 = reserved
 180                  * [11: 6] Reserved
 181                  * [24:12] PCI I/O Limit Address i
 182                  *         This field defines the end of PCI I/O region n
 183                  * [31:25] Reserved
 184                  */
 185                 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
 186                 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001,
 187                 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 188                 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 189
 190                 /* PCI I/O Base i Registers
 191                  * F1:0xC0 i = 0
 192                  * F1:0xC8 i = 1
 193                  * F1:0xD0 i = 2
 194                  * F1:0xD8 i = 3
 195                  * [ 0: 0] Read Enable
 196                  *         0 = Reads Disabled
 197                  *         1 = Reads Enabled
 198                  * [ 1: 1] Write Enable
 199                  *         0 = Writes Disabled
 200                  *         1 = Writes Enabled
 201                  * [ 3: 2] Reserved
 202                  * [ 4: 4] VGA Enable
 203                  *         0 = VGA matches Disabled
 204                  *         1 = matches all address < 64K and where A[9:0] is in the
 205                  *             range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 206                  * [ 5: 5] ISA Enable
 207                  *         0 = ISA matches Disabled
 208                  *         1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
 209                  *             from matching agains this base/limit pair
 210                  * [11: 6] Reserved
 211                  * [24:12] PCI I/O Base i
 212                  *         This field defines the start of PCI I/O region n
 213                  * [31:25] Reserved
 214                  */
 215                 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
 216                 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
 217                 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 218                 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
 219
 220                 /* Config Base and Limit i Registers
 221                  * F1:0xE0 i = 0
 222                  * F1:0xE4 i = 1
 223                  * F1:0xE8 i = 2
 224                  * F1:0xEC i = 3
 225                  * [ 0: 0] Read Enable
 226                  *         0 = Reads Disabled
 227                  *         1 = Reads Enabled
 228                  * [ 1: 1] Write Enable
 229                  *         0 = Writes Disabled
 230                  *         1 = Writes Enabled
 231                  * [ 2: 2] Device Number Compare Enable
 232                  *         0 = The ranges are based on bus number
 233                  *         1 = The ranges are ranges of devices on bus 0
 234                  * [ 3: 3] Reserved
 235                  * [ 6: 4] Destination Node
 236                  *         000 = Node 0
 237                  *         001 = Node 1
 238                  *         010 = Node 2
 239                  *         011 = Node 3
 240                  *         100 = Node 4
 241                  *         101 = Node 5
 242                  *         110 = Node 6
 243                  *         111 = Node 7
 244                  * [ 7: 7] Reserved
 245                  * [ 9: 8] Destination Link
 246                  *         00 = Link 0
 247                  *         01 = Link 1
 248                  *         10 = Link 2
 249                  *         11 - Reserved
 250                  * [15:10] Reserved
 251                  * [23:16] Bus Number Base i
 252                  *         This field defines the lowest bus number in configuration region i
 253                  * [31:24] Bus Number Limit i
 254                  *         This field defines the highest bus number in configuration region i
 255                  */
 256                 PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103,
 257                 PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113,
 258                 PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000, 0x00000000,
 259                 PCI_ADDR(0, 0x18, 1, 0xec), 0x0000, 0x00000000,
 260         };
 261
 262         int max;
 263         max = sizeof(register_values)/sizeof(register_values[0]);
 264         setup_resource_map(register_values, max);
 265 }
 266