1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #include <cpu/amd/amdk8_sysconf.h>
8 extern unsigned char bus_isa;
9 extern unsigned char bus_ck804_0; //1
10 extern unsigned char bus_ck804_1; //2
11 extern unsigned char bus_ck804_2; //3
12 extern unsigned char bus_ck804_3; //4
13 extern unsigned char bus_ck804_4; //5
14 extern unsigned char bus_ck804_5; //6
15 extern unsigned char bus_8131_0; //7
16 extern unsigned char bus_8131_1; //8
17 extern unsigned char bus_8131_2; //9
18 extern unsigned char bus_ck804b_0;//a
19 extern unsigned char bus_ck804b_1;//b
20 extern unsigned char bus_ck804b_2;//c
21 extern unsigned char bus_ck804b_3;//d
22 extern unsigned char bus_ck804b_4;//e
23 extern unsigned char bus_ck804b_5;//f
24 extern unsigned apicid_ck804;
25 extern unsigned apicid_8131_1;
26 extern unsigned apicid_8131_2;
27 extern unsigned apicid_ck804b;
29 extern unsigned pci1234[];
32 extern unsigned hcdn[];
33 extern unsigned sbdn3;
34 extern unsigned sbdnb;
36 static void *smp_write_config_table(void *v)
38 struct mp_config_table *mc;
39 unsigned char bus_num;
42 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
44 mptable_init(mc, "Ultra40 ", LAPIC_ADDR);
46 smp_write_processors(mc);
51 /* define bus and isa numbers */
52 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
53 smp_write_bus(mc, bus_num, "PCI ");
55 smp_write_bus(mc, bus_isa, "ISA ");
57 /*I/O APICs: APIC ID Version State Address*/
63 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
65 res = find_resource(dev, PCI_BASE_ADDRESS_1);
67 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
70 /* Initialize interrupt mapping*/
73 pci_write_config32(dev, 0x7c, dword);
76 pci_write_config32(dev, 0x80, dword);
79 pci_write_config32(dev, 0x84, dword);
83 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
85 res = find_resource(dev, PCI_BASE_ADDRESS_0);
87 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
90 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
92 res = find_resource(dev, PCI_BASE_ADDRESS_0);
94 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
98 if(pci1234[2] & 0xf) {
99 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
101 res = find_resource(dev, PCI_BASE_ADDRESS_1);
103 smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
107 pci_write_config32(dev, 0x7c, dword);
110 pci_write_config32(dev, 0x80, dword);
113 pci_write_config32(dev, 0x84, dword);
120 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
122 // Onboard ck804 smbus
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
126 // Onboard ck804 USB 1.1
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
129 // Onboard ck804 USB 2
130 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
132 // Onboard ck804 Audio
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
135 // Onboard ck804 SATA 0
136 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
138 // Onboard ck804 SATA 1
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
157 if(pci1234[2] & 0xf) {
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
169 //Slot 4 PCI-X 100/66
171 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
186 //Slot 6 PCIX 133/100/66
188 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
191 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
192 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
193 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
194 /* There is no extension information... */
196 /* Compute the checksums */
197 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
198 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
199 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
200 mc, smp_next_mpe_entry(mc));
201 return smp_next_mpe_entry(mc);
204 unsigned long write_smp_table(unsigned long addr)
207 v = smp_write_floating_table(addr);
208 return (unsigned long)smp_write_config_table(v);