1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #include <cpu/amd/amdk8_sysconf.h>
8 extern unsigned char bus_ck804_0; //1
9 extern unsigned char bus_ck804_1; //2
10 extern unsigned char bus_ck804_2; //3
11 extern unsigned char bus_ck804_3; //4
12 extern unsigned char bus_ck804_4; //5
13 extern unsigned char bus_ck804_5; //6
14 extern unsigned char bus_8131_0; //7
15 extern unsigned char bus_8131_1; //8
16 extern unsigned char bus_8131_2; //9
17 extern unsigned char bus_ck804b_0;//a
18 extern unsigned char bus_ck804b_1;//b
19 extern unsigned char bus_ck804b_2;//c
20 extern unsigned char bus_ck804b_3;//d
21 extern unsigned char bus_ck804b_4;//e
22 extern unsigned char bus_ck804b_5;//f
23 extern unsigned apicid_ck804;
24 extern unsigned apicid_8131_1;
25 extern unsigned apicid_8131_2;
26 extern unsigned apicid_ck804b;
28 extern unsigned pci1234[];
31 extern unsigned hcdn[];
32 extern unsigned sbdn3;
33 extern unsigned sbdnb;
35 static void *smp_write_config_table(void *v)
37 struct mp_config_table *mc;
40 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
42 mptable_init(mc, LAPIC_ADDR);
44 smp_write_processors(mc);
48 mptable_write_buses(mc, NULL, &bus_isa);
50 /*I/O APICs: APIC ID Version State Address*/
56 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
58 res = find_resource(dev, PCI_BASE_ADDRESS_1);
60 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
63 /* Initialize interrupt mapping*/
66 pci_write_config32(dev, 0x7c, dword);
69 pci_write_config32(dev, 0x80, dword);
72 pci_write_config32(dev, 0x84, dword);
76 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
78 res = find_resource(dev, PCI_BASE_ADDRESS_0);
80 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
83 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
85 res = find_resource(dev, PCI_BASE_ADDRESS_0);
87 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
91 if(pci1234[2] & 0xf) {
92 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
94 res = find_resource(dev, PCI_BASE_ADDRESS_1);
96 smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
100 pci_write_config32(dev, 0x7c, dword);
103 pci_write_config32(dev, 0x80, dword);
106 pci_write_config32(dev, 0x84, dword);
113 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
115 // Onboard ck804 smbus
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
119 // Onboard ck804 USB 1.1
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
122 // Onboard ck804 USB 2
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
125 // Onboard ck804 Audio
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
128 // Onboard ck804 SATA 0
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
131 // Onboard ck804 SATA 1
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
150 if(pci1234[2] & 0xf) {
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
162 //Slot 4 PCI-X 100/66
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
179 //Slot 6 PCIX 133/100/66
181 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
184 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
185 mptable_lintsrc(mc, bus_isa);
186 /* There is no extension information... */
188 /* Compute the checksums */
189 return mptable_finalize(mc);
192 unsigned long write_smp_table(unsigned long addr)
195 v = smp_write_floating_table(addr, 0);
196 return (unsigned long)smp_write_config_table(v);