1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 extern unsigned char bus_isa;
8 extern unsigned char bus_ck804_0; //1
9 extern unsigned char bus_ck804_1; //2
10 extern unsigned char bus_ck804_2; //3
11 extern unsigned char bus_ck804_3; //4
12 extern unsigned char bus_ck804_4; //5
13 extern unsigned char bus_ck804_5; //6
14 extern unsigned char bus_8131_0; //7
15 extern unsigned char bus_8131_1; //8
16 extern unsigned char bus_8131_2; //9
17 extern unsigned char bus_ck804b_0;//a
18 extern unsigned char bus_ck804b_1;//b
19 extern unsigned char bus_ck804b_2;//c
20 extern unsigned char bus_ck804b_3;//d
21 extern unsigned char bus_ck804b_4;//e
22 extern unsigned char bus_ck804b_5;//f
23 extern unsigned apicid_ck804;
24 extern unsigned apicid_8131_1;
25 extern unsigned apicid_8131_2;
26 extern unsigned apicid_ck804b;
28 extern unsigned pci1234[];
31 extern unsigned hcdn[];
32 extern unsigned sbdn3;
33 extern unsigned sbdnb;
35 extern void get_bus_conf(void);
37 static void *smp_write_config_table(void *v)
39 static const char sig[4] = "PCMP";
40 static const char oem[8] = "SUNW ";
41 static const char productid[12] = "ultra40 ";
42 struct mp_config_table *mc;
44 unsigned char bus_num;
47 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
48 memset(mc, 0, sizeof(*mc));
50 memcpy(mc->mpc_signature, sig, sizeof(sig));
51 mc->mpc_length = sizeof(*mc); /* initially just the header */
53 mc->mpc_checksum = 0; /* not yet computed */
54 memcpy(mc->mpc_oem, oem, sizeof(oem));
55 memcpy(mc->mpc_productid, productid, sizeof(productid));
58 mc->mpc_entry_count = 0; /* No entries yet... */
59 mc->mpc_lapic = LAPIC_ADDR;
64 smp_write_processors(mc);
69 /* define bus and isa numbers */
70 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
71 smp_write_bus(mc, bus_num, "PCI ");
73 smp_write_bus(mc, bus_isa, "ISA ");
75 /*I/O APICs: APIC ID Version State Address*/
81 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
83 res = find_resource(dev, PCI_BASE_ADDRESS_1);
85 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
88 /* Initialize interrupt mapping*/
91 pci_write_config32(dev, 0x7c, dword);
94 pci_write_config32(dev, 0x80, dword);
97 pci_write_config32(dev, 0x84, dword);
101 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
103 res = find_resource(dev, PCI_BASE_ADDRESS_0);
105 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
108 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
110 res = find_resource(dev, PCI_BASE_ADDRESS_0);
112 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
116 if(pci1234[2] & 0xf) {
117 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
119 res = find_resource(dev, PCI_BASE_ADDRESS_1);
121 smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
125 pci_write_config32(dev, 0x7c, dword);
128 pci_write_config32(dev, 0x80, dword);
131 pci_write_config32(dev, 0x84, dword);
138 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
139 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1);
141 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x2);
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_ck804, 0x3);
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_ck804, 0x4);
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_ck804, 0x6);
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_ck804, 0x7);
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_ck804, 0x8);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_ck804, 0xc);
148 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_ck804, 0xd);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_ck804, 0xe);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
152 // Onboard ck804 smbus
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
156 // Onboard ck804 USB 1.1
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
159 // Onboard ck804 USB 2
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
162 // Onboard ck804 Audio
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
165 // Onboard ck804 SATA 0
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
168 // Onboard ck804 SATA 1
169 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
184 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
187 if(pci1234[2] & 0xf) {
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
193 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
199 //Slot 4 PCI-X 100/66
201 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
206 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
211 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
216 //Slot 6 PCIX 133/100/66
218 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
221 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
222 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
223 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
224 /* There is no extension information... */
226 /* Compute the checksums */
227 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
228 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
229 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
230 mc, smp_next_mpe_entry(mc));
231 return smp_next_mpe_entry(mc);
234 unsigned long write_smp_table(unsigned long addr)
237 v = smp_write_floating_table(addr);
238 return (unsigned long)smp_write_config_table(v);