src/mainboard/sunw/ultra40/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4
   5 #define K8_ALLOCATE_IO_RANGE 1
   6 //#define K8_SCAN_PCI_BUS 1
   7
   8
   9 #define QRANK_DIMM_SUPPORT 1
  10
  11 #if CONFIG_LOGICAL_CPUS==1
  12 #define SET_NB_CFG_54 1
  13 #endif
  14
  15
  16 #include <stdint.h>
  17 #include <string.h>
  18 #include <device/pci_def.h>
  19 #include <arch/io.h>
  20 #include <device/pnp_def.h>
  21 #include <arch/romcc_io.h>
  22 #include <cpu/x86/lapic.h>
  23 #include "option_table.h"
  24 #include "pc80/mc146818rtc_early.c"
  25 #include "pc80/serial.c"
  26 #include "arch/i386/lib/console.c"
  27 #include "ram/ramtest.c"
  28
  29 #include <cpu/amd/model_fxx_rev.h>
  30 #include "northbridge/amd/amdk8/incoherent_ht.c"
  31 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  32 #include "northbridge/amd/amdk8/raminit.h"
  33 #include "cpu/amd/model_fxx/apic_timer.c"
  34 #include "lib/delay.c"
  35
  36 #include "cpu/x86/lapic/boot_cpu.c"
  37 #include "northbridge/amd/amdk8/reset_test.c"
  38 #include "northbridge/amd/amdk8/debug.c"
  39 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  40
  41 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  42 #include "cpu/x86/bist.h"
  43
  44 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  45
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47
  48 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  49
  50 static void memreset_setup(void)
  51 {
  52 }
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl)
  55 {
  56 }
  57
  58 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  59
  60 #define SUPERIO_GPIO_IO_BASE 0x400
  61
  62 static void sio_gpio_setup(void){
  63
  64         unsigned value;
  65
  66         /*Enable onboard scsi*/
  67         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  68         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  69         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  70
  71 }
  72
  73 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  74 {
  75         /* nothing to do */
  76 }
  77
  78 static inline int spd_read_byte(unsigned device, unsigned address)
  79 {
  80         return smbus_read_byte(device, address);
  81 }
  82
  83
  84 #include "northbridge/amd/amdk8/raminit.c"
  85 #include "northbridge/amd/amdk8/coherent_ht.c"
  86 #include "sdram/generic_sdram.c"
  87
  88  /* tyan does not want the default */
  89 #include "resourcemap.c"
  90
  91 #include "cpu/amd/dualcore/dualcore.c"
  92
  93 #define CK804_NUM 2
  94 #define CK804_USE_NIC 1
  95 #define CK804_USE_ACI 1
  96
  97 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  98
  99 //set GPIO to input mode
 100 #define CK804_MB_SETUP \
 101                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 102                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 103                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 104                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 105                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 106                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 107
 108 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 109
 110 #include "cpu/amd/car/copy_and_run.c"
 111
 112 #include "cpu/amd/car/post_cache_as_ram.c"
 113
 114 #include "cpu/amd/model_fxx/init_cpus.c"
 115
 116
 117 #if USE_FALLBACK_IMAGE == 1
 118
 119 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 120 #include "northbridge/amd/amdk8/early_ht.c"
 121
 122
 123 static void sio_setup(void)
 124 {
 125
 126         unsigned value;
 127         uint32_t dword;
 128         uint8_t byte;
 129
 130
 131         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 132
 133         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 134         byte |= 0x20;
 135         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 136
 137         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 138         dword |= (1<<29)|(1<<0);
 139         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 140
 141 #if  1
 142         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 143
 144         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 145         value &= 0xbf;
 146         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 147 #endif
 148
 149 }
 150
 151 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 152 {
 153         unsigned last_boot_normal_x = last_boot_normal();
 154
 155         /* Is this a cpu only reset? or Is this a secondary cpu? */
 156         if ((cpu_init_detectedx) || (!boot_cpu())) {
 157                 if (last_boot_normal_x) {
 158                         goto normal_image;
 159                 } else {
 160                         goto fallback_image;
 161                 }
 162         }
 163
 164         /* Nothing special needs to be done to find bus 0 */
 165         /* Allow the HT devices to be found */
 166
 167         enumerate_ht_chain();
 168
 169         sio_setup();
 170
 171         /* Setup the ck804 */
 172         ck804_enable_rom();
 173
 174         /* Is this a deliberate reset by the bios */
 175         if (bios_reset_detected() && last_boot_normal_x) {
 176                 goto normal_image;
 177         }
 178         /* This is the primary cpu how should I boot? */
 179         else if (do_normal_boot()) {
 180                 goto normal_image;
 181         }
 182         else {
 183                 goto fallback_image;
 184         }
 185  normal_image:
 186         __asm__ volatile ("jmp __normal_image"
 187                 : /* outputs */
 188                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 189                 );
 190
 191  fallback_image:
 192         ;
 193 }
 194 #endif
 195
 196 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 197
 198 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 199 {
 200
 201 #if USE_FALLBACK_IMAGE == 1
 202         failover_process(bist, cpu_init_detectedx);
 203 #endif
 204         real_main(bist, cpu_init_detectedx);
 205
 206 }
 207
 208 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 209 {
 210         static const uint16_t spd_addr [] = {
 211                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 212                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 213 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 214                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 215                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 216 #endif
 217         };
 218
 219         int needs_reset;
 220         unsigned bsp_apicid = 0;
 221
 222         struct mem_controller ctrl[8];
 223         unsigned nodes;
 224
 225         if (bist == 0) {
 226                 bsp_apicid = init_cpus(cpu_init_detectedx);
 227         }
 228
 229         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 230         uart_init();
 231         console_init();
 232
 233         /* Halt if there was a built in self test failure */
 234         report_bist_failure(bist);
 235
 236         setup_ultra40_resource_map();
 237
 238         needs_reset = setup_coherent_ht_domain();
 239
 240         wait_all_core0_started();
 241 #if CONFIG_LOGICAL_CPUS==1
 242         // It is said that we should start core1 after all core0 launched
 243         start_other_cores();
 244         wait_all_other_cores_started(bsp_apicid);
 245 #endif
 246
 247         needs_reset |= ht_setup_chains_x();
 248
 249         needs_reset |= ck804_early_setup_x();
 250
 251         if (needs_reset) {
 252                 print_info("ht reset -\r\n");
 253                 soft_reset();
 254         }
 255
 256         allow_all_aps_stop(bsp_apicid);
 257
 258         nodes = get_nodes();
 259         //It's the time to set ctrl now;
 260         fill_mem_ctrl(nodes, ctrl, spd_addr);
 261
 262         enable_smbus();
 263
 264         memreset_setup();
 265         sdram_initialize(nodes, ctrl);
 266
 267         post_cache_as_ram();
 268 }