src/mainboard/sunw/ultra40/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4
   5 #define K8_ALLOCATE_IO_RANGE 1
   6
   7 #define QRANK_DIMM_SUPPORT 1
   8
   9 #if CONFIG_LOGICAL_CPUS==1
  10 #define SET_NB_CFG_54 1
  11 #endif
  12
  13
  14 #include <stdint.h>
  15 #include <string.h>
  16 #include <device/pci_def.h>
  17 #include <arch/io.h>
  18 #include <device/pnp_def.h>
  19 #include <arch/romcc_io.h>
  20 #include <cpu/x86/lapic.h>
  21 #include "option_table.h"
  22 #include "pc80/mc146818rtc_early.c"
  23 #include "pc80/serial.c"
  24 #include "arch/i386/lib/console.c"
  25 #include "lib/ramtest.c"
  26
  27 #include <cpu/amd/model_fxx_rev.h>
  28 #include "northbridge/amd/amdk8/incoherent_ht.c"
  29 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32 #include "lib/delay.c"
  33
  34 #include "cpu/x86/lapic/boot_cpu.c"
  35 #include "northbridge/amd/amdk8/reset_test.c"
  36 #include "northbridge/amd/amdk8/debug.c"
  37 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  38
  39 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  40 #include "cpu/x86/bist.h"
  41
  42 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  43
  44 #include "northbridge/amd/amdk8/setup_resource_map.c"
  45
  46 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  47
  48 static void memreset_setup(void)
  49 {
  50 }
  51
  52 static void memreset(int controllers, const struct mem_controller *ctrl)
  53 {
  54 }
  55
  56 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  57
  58 #define SUPERIO_GPIO_IO_BASE 0x400
  59
  60 static void sio_gpio_setup(void){
  61
  62         unsigned value;
  63
  64         /*Enable onboard scsi*/
  65         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  66         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  67         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  68
  69 }
  70
  71 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  72 {
  73         /* nothing to do */
  74 }
  75
  76 static inline int spd_read_byte(unsigned device, unsigned address)
  77 {
  78         return smbus_read_byte(device, address);
  79 }
  80
  81
  82 #include "northbridge/amd/amdk8/raminit.c"
  83 #include "northbridge/amd/amdk8/coherent_ht.c"
  84 #include "lib/generic_sdram.c"
  85
  86  /* tyan does not want the default */
  87 #include "resourcemap.c"
  88
  89 #include "cpu/amd/dualcore/dualcore.c"
  90
  91 #define CK804_NUM 2
  92 #define CK804_USE_NIC 1
  93 #define CK804_USE_ACI 1
  94
  95 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  96
  97 //set GPIO to input mode
  98 #define CK804_MB_SETUP \
  99                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 100                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 101                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 102                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 103                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 104                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 105
 106 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 107
 108 #include "cpu/amd/car/copy_and_run.c"
 109
 110 #include "cpu/amd/car/post_cache_as_ram.c"
 111
 112 #include "cpu/amd/model_fxx/init_cpus.c"
 113
 114
 115 #if CONFIG_USE_FALLBACK_IMAGE == 1
 116
 117 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 118 #include "northbridge/amd/amdk8/early_ht.c"
 119
 120
 121 static void sio_setup(void)
 122 {
 123
 124         unsigned value;
 125         uint32_t dword;
 126         uint8_t byte;
 127
 128
 129         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 130
 131         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 132         byte |= 0x20;
 133         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 134
 135         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 136         dword |= (1<<29)|(1<<0);
 137         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 138
 139 #if  1
 140         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 141
 142         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 143         value &= 0xbf;
 144         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 145 #endif
 146
 147 }
 148
 149 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 150 {
 151         unsigned last_boot_normal_x = last_boot_normal();
 152
 153         /* Is this a cpu only reset? or Is this a secondary cpu? */
 154         if ((cpu_init_detectedx) || (!boot_cpu())) {
 155                 if (last_boot_normal_x) {
 156                         goto normal_image;
 157                 } else {
 158                         goto fallback_image;
 159                 }
 160         }
 161
 162         /* Nothing special needs to be done to find bus 0 */
 163         /* Allow the HT devices to be found */
 164
 165         enumerate_ht_chain();
 166
 167         sio_setup();
 168
 169         /* Setup the ck804 */
 170         ck804_enable_rom();
 171
 172         /* Is this a deliberate reset by the bios */
 173         if (bios_reset_detected() && last_boot_normal_x) {
 174                 goto normal_image;
 175         }
 176         /* This is the primary cpu how should I boot? */
 177         else if (do_normal_boot()) {
 178                 goto normal_image;
 179         }
 180         else {
 181                 goto fallback_image;
 182         }
 183  normal_image:
 184         __asm__ volatile ("jmp __normal_image"
 185                 : /* outputs */
 186                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 187                 );
 188
 189  fallback_image:
 190         ;
 191 }
 192 #endif
 193
 194 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 195
 196 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 197 {
 198
 199 #if CONFIG_USE_FALLBACK_IMAGE == 1
 200         failover_process(bist, cpu_init_detectedx);
 201 #endif
 202         real_main(bist, cpu_init_detectedx);
 203
 204 }
 205
 206 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 207 {
 208         static const uint16_t spd_addr [] = {
 209                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 210                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 211 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 212                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 213                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 214 #endif
 215         };
 216
 217         int needs_reset;
 218         unsigned bsp_apicid = 0;
 219
 220         struct mem_controller ctrl[8];
 221         unsigned nodes;
 222
 223         if (bist == 0) {
 224                 bsp_apicid = init_cpus(cpu_init_detectedx);
 225         }
 226
 227         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 228         uart_init();
 229         console_init();
 230
 231         /* Halt if there was a built in self test failure */
 232         report_bist_failure(bist);
 233
 234         setup_ultra40_resource_map();
 235
 236         needs_reset = setup_coherent_ht_domain();
 237
 238         wait_all_core0_started();
 239 #if CONFIG_LOGICAL_CPUS==1
 240         // It is said that we should start core1 after all core0 launched
 241         start_other_cores();
 242         wait_all_other_cores_started(bsp_apicid);
 243 #endif
 244
 245         needs_reset |= ht_setup_chains_x();
 246
 247         needs_reset |= ck804_early_setup_x();
 248
 249         if (needs_reset) {
 250                 print_info("ht reset -\r\n");
 251                 soft_reset();
 252         }
 253
 254         allow_all_aps_stop(bsp_apicid);
 255
 256         nodes = get_nodes();
 257         //It's the time to set ctrl now;
 258         fill_mem_ctrl(nodes, ctrl, spd_addr);
 259
 260         enable_smbus();
 261
 262         memreset_setup();
 263         sdram_initialize(nodes, ctrl);
 264
 265         post_cache_as_ram();
 266 }