src/mainboard/sunw/ultra40/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 //#define K8_HT_FREQ_1G_SUPPORT 1
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23 #include "cpu/x86/lapic/boot_cpu.c"
  24 #include "northbridge/amd/amdk8/reset_test.c"
  25 #include "northbridge/amd/amdk8/debug.c"
  26 #include <cpu/amd/model_fxx_msr.h>
  27 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  28
  29 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  30 #include "cpu/x86/bist.h"
  31 #include "cpu/amd/dualcore/dualcore.c"
  32
  33 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  38
  39 static void hard_reset(void)
  40 {
  41         set_bios_reset();
  42
  43         /* full reset */
  44         outb(0x0a, 0x0cf9);
  45         outb(0x0e, 0x0cf9);
  46 }
  47
  48 static void soft_reset(void)
  49 {
  50         set_bios_reset();
  51 #if 1
  52         /* link reset */
  53         outb(0x02, 0x0cf9);
  54         outb(0x06, 0x0cf9);
  55 #endif
  56 }
  57
  58 static void memreset_setup(void)
  59 {
  60 }
  61
  62 static void memreset(int controllers, const struct mem_controller *ctrl)
  63 {
  64 }
  65
  66 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  67
  68 #define SUPERIO_GPIO_IO_BASE 0x400
  69
  70 static void sio_gpio_setup(void){
  71
  72         unsigned value;
  73
  74 //      lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
  75
  76 #if 1
  77         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  78         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  79         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  80 #endif
  81
  82 }
  83
  84 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  85 {
  86         /* nothing to do */
  87 }
  88
  89 static inline int spd_read_byte(unsigned device, unsigned address)
  90 {
  91         return smbus_read_byte(device, address);
  92 }
  93
  94 #define QRANK_DIMM_SUPPORT 1
  95
  96 #include "northbridge/amd/amdk8/raminit.c"
  97 #if 0
  98         #define ENABLE_APIC_EXT_ID 1
  99         #define APIC_ID_OFFSET 0x10
 100         #define LIFT_BSP_APIC_ID 0
 101 #else
 102         #define ENABLE_APIC_EXT_ID 0
 103 #endif
 104 #include "northbridge/amd/amdk8/coherent_ht.c"
 105 #include "sdram/generic_sdram.c"
 106
 107 /* maybe does not want the default */
 108 #include "resourcemap.c"
 109
 110
 111 #define FIRST_CPU  1
 112 #define SECOND_CPU 1
 113 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 114
 115 #define CK804_NUM 2
 116 #define CK804B_BUSN 0x80
 117 #define CK804_USE_NIC 1
 118 #define CK804_USE_ACI 1
 119 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 120
 121 //set GPIO to input mode
 122 #define CK804_MB_SETUP \
 123                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 124                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 125                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 126                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 127                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 128                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 129
 130 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 131
 132
 133 static void main(unsigned long bist)
 134 {
 135         static const struct mem_controller cpu[] = {
 136 #if FIRST_CPU
 137                 {
 138                         .node_id = 0,
 139                         .f0 = PCI_DEV(0, 0x18, 0),
 140                         .f1 = PCI_DEV(0, 0x18, 1),
 141                         .f2 = PCI_DEV(0, 0x18, 2),
 142                         .f3 = PCI_DEV(0, 0x18, 3),
 143                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 144                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 145                 },
 146 #endif
 147 #if SECOND_CPU
 148                 {
 149                         .node_id = 1,
 150                         .f0 = PCI_DEV(0, 0x19, 0),
 151                         .f1 = PCI_DEV(0, 0x19, 1),
 152                         .f2 = PCI_DEV(0, 0x19, 2),
 153                         .f3 = PCI_DEV(0, 0x19, 3),
 154                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 155                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 156                 },
 157 #endif
 158         };
 159
 160         int needs_reset;
 161
 162         if (bist == 0) {
 163                 k8_init_and_stop_secondaries();
 164         }
 165
 166         // post_code(0x32);
 167
 168         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 169         uart_init();
 170         console_init();
 171
 172         /* Halt if there was a built in self test failure */
 173         report_bist_failure(bist);
 174
 175         sio_gpio_setup();
 176
 177         setup_ultra40_resource_map();
 178
 179         needs_reset = setup_coherent_ht_domain();
 180
 181         needs_reset |= ht_setup_chains_x();
 182
 183         needs_reset |= ck804_early_setup_x();
 184
 185         if (needs_reset) {
 186                 print_info("ht reset -\r\n");
 187                 soft_reset();
 188         }
 189
 190
 191         enable_smbus();
 192
 193         memreset_setup();
 194         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 195
 196
 197 }