src/mainboard/sunw/ultra40/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19 default CONFIG_ROM_PAYLOAD     = 1
  20
  21 ##
  22 ## Compute where this copy of coreboot will start in the boot rom
  23 ##
  24 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  25
  26 ##
  27 ## Compute a range of ROM that can cached to speed up coreboot,
  28 ## execution speed.
  29 ##
  30 ## XIP_ROM_SIZE must be a power of 2.
  31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  32 ##
  33 default XIP_ROM_SIZE=65536
  34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  35
  36 arch i386 end
  37
  38
  39 ##
  40 ## Build the objects we have code for in this directory.
  41 ##
  42
  43 driver mainboard.o
  44 #needed by irq_tables and mptable and acpi_tables
  45 object get_bus_conf.o
  46
  47 if HAVE_MP_TABLE object mptable.o end
  48 if HAVE_PIRQ_TABLE object irq_tables.o end
  49 #object reset.o
  50         if CONFIG_USE_INIT
  51                 makerule ./auto.o
  52                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  53                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  54                 end
  55         else
  56                 makerule ./auto.inc
  57                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  58                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
  59                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  60                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  61                 end
  62         end
  63
  64 ##
  65 ## Build our 16 bit and 32 bit coreboot entry code
  66 ##
  67 if USE_FALLBACK_IMAGE
  68         mainboardinit cpu/x86/16bit/entry16.inc
  69         ldscript /cpu/x86/16bit/entry16.lds
  70 end
  71
  72 mainboardinit cpu/x86/32bit/entry32.inc
  73
  74         if CONFIG_USE_INIT
  75                 ldscript /cpu/x86/32bit/entry32.lds
  76         end
  77
  78         if CONFIG_USE_INIT
  79                 ldscript /cpu/amd/car/cache_as_ram.lds
  80         end
  81
  82 ##
  83 ## Build our reset vector (This is where coreboot is entered)
  84 ##
  85 if USE_FALLBACK_IMAGE
  86         mainboardinit cpu/x86/16bit/reset16.inc
  87         ldscript /cpu/x86/16bit/reset16.lds
  88 else
  89         mainboardinit cpu/x86/32bit/reset32.inc
  90         ldscript /cpu/x86/32bit/reset32.lds
  91 end
  92
  93 ##
  94 ## Include an id string (For safe flashing)
  95 ##
  96 mainboardinit southbridge/nvidia/ck804/id.inc
  97 ldscript /southbridge/nvidia/ck804/id.lds
  98
  99 ##
 100 ## ROMSTRAP table for CK804
 101 ##
 102 if USE_FALLBACK_IMAGE
 103         mainboardinit southbridge/nvidia/ck804/romstrap.inc
 104         ldscript /southbridge/nvidia/ck804/romstrap.lds
 105 end
 106
 107         ##
 108         ## Setup Cache-As-Ram
 109         ##
 110         mainboardinit cpu/amd/car/cache_as_ram.inc
 111
 112 ###
 113 ### This is the early phase of coreboot startup
 114 ### Things are delicate and we test to see if we should
 115 ### failover to another image.
 116 ###
 117 if USE_FALLBACK_IMAGE
 118         ldscript /arch/i386/lib/failover.lds
 119 end
 120
 121 ##
 122 ## Setup RAM
 123 ##
 124         if CONFIG_USE_INIT
 125                 initobject auto.o
 126         else
 127                 mainboardinit ./auto.inc
 128         end
 129
 130 ##
 131 ## Include the secondary Configuration files
 132 ##
 133 config chip.h
 134
 135 # sample config for tyan/s2895
 136 chip northbridge/amd/amdk8/root_complex
 137         device apic_cluster 0 on
 138                 chip cpu/amd/socket_940
 139                         device apic 0 on end
 140                 end
 141         end
 142         device pci_domain 0 on
 143                 chip northbridge/amd/amdk8 #mc0
 144                         device pci 18.0 on end # link 0
 145                         device pci 18.0 on # link1
 146                                 #  devices on link 0, link 0 == LDT 0
 147                                 chip southbridge/nvidia/ck804
 148                                         device pci 0.0 on end   # HT
 149                                         device pci 1.0 on # LPC
 150                                                 chip superio/smsc/lpc47m10x
 151                                                         device pnp 2e.0 off #  Floppy
 152                                                                  io 0x60 = 0x3f0
 153                                                                 irq 0x70 = 6
 154                                                                 drq 0x74 = 2
 155                                                         end
 156                                                         device pnp 2e.3 off #  Parallel Port
 157                                                                  io 0x60 = 0x378
 158                                                                 irq 0x70 = 7
 159                                                         end
 160                                                         device pnp 2e.4 on #  Com1
 161                                                                 io 0x60 = 0x3f8
 162                                                                 irq 0x70 = 4
 163                                                         end
 164                                                         device pnp 2e.5 off #  Com2
 165                                                                 io 0x60 = 0x2f8
 166                                                                 irq 0x70 = 3
 167                                                         end
 168                                                         device pnp 2e.7 off #  Keyboard
 169                                                                 io 0x60 = 0x60
 170                                                                 io 0x62 = 0x64
 171                                                                 irq 0x70 = 1
 172                                                                 irq 0x72 = 12
 173                                                         end
 174                                                 end
 175                                         end
 176                                         device pci 1.1 on # SM 0
 177                                                 chip drivers/generic/generic #dimm 0-0-0
 178                                                         device i2c 50 on end
 179                                                 end
 180                                                 chip drivers/generic/generic #dimm 0-0-1
 181                                                         device i2c 51 on end
 182                                                 end
 183                                                 chip drivers/generic/generic #dimm 0-1-0
 184                                                         device i2c 52 on end
 185                                                 end
 186                                                 chip drivers/generic/generic #dimm 0-1-1
 187                                                         device i2c 53 on end
 188                                                 end
 189                                                 chip drivers/generic/generic #dimm 1-0-0
 190                                                         device i2c 54 on end
 191                                                 end
 192                                                 chip drivers/generic/generic #dimm 1-0-1
 193                                                         device i2c 55 on end
 194                                                 end
 195                                                 chip drivers/generic/generic #dimm 1-1-0
 196                                                         device i2c 56 on end
 197                                                 end
 198                                                 chip drivers/generic/generic #dimm 1-1-1
 199                                                         device i2c 57 on end
 200                                                 end
 201                                         end # SM
 202                                         device pci 1.1 on # SM 1
 203 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 204 #                                                chip drivers/generic/generic #PCIXA Slot1
 205 #                                                        device i2c 50 on end
 206 #                                                end
 207 #                                                chip drivers/generic/generic #PCIXB Slot1
 208 #                                                        device i2c 51 on end
 209 #                                                end
 210 #                                                chip drivers/generic/generic #PCIXB Slot2
 211 #                                                        device i2c 52 on end
 212 #                                                end
 213 #                                                chip drivers/generic/generic #PCI Slot1
 214 #                                                        device i2c 53 on end
 215 #                                                end
 216 #                                                chip drivers/generic/generic #Master CK804 PCI-E
 217 #                                                        device i2c 54 on end
 218 #                                                end
 219 #                                                chip drivers/generic/generic #Slave CK804 PCI-E
 220 #                                                        device i2c 55 on end
 221 #                                                end
 222                                                 chip drivers/generic/generic #MAC EEPROM
 223                                                         device i2c 51 on end
 224                                                 end
 225
 226                                         end # SM
 227                                         device pci 2.0 on end # USB 1.1
 228                                         device pci 2.1 on end # USB 2
 229                                         device pci 4.0 on end # ACI
 230                                         device pci 4.1 off end # MCI
 231                                         device pci 6.0 on end # IDE
 232                                         device pci 7.0 on end # SATA 1
 233                                         device pci 8.0 on end # SATA 0
 234                                         device pci 9.0 on end # PCI
 235                                         device pci a.0 on end # NIC
 236                                         device pci b.0 off end # PCI E 3
 237                                         device pci c.0 off end # PCI E 2
 238                                         device pci d.0 off end # PCI E 1
 239                                         device pci e.0 on end # PCI E 0
 240                                         register "ide0_enable" = "1"
 241                                         register "ide1_enable" = "1"
 242                                         register "sata0_enable" = "1"
 243                                         register "sata1_enable" = "1"
 244 #                                       register "nic_rom_address" = "0xfff80000" # 64k
 245 #                                       register "raid_rom_address" = "0xfff90000"
 246                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 247                                         register "mac_eeprom_addr" = "0x51"
 248                                 end
 249                         end #  device pci 18.0
 250                         device pci 18.0 on end # link 2
 251                         device pci 18.1 on end
 252                         device pci 18.2 on end
 253                         device pci 18.3 on end
 254                 end # mc0
 255
 256                 chip northbridge/amd/amdk8
 257                         device pci 19.0 on end # link 0
 258                 device pci 19.0 on
 259                                 #  devices on link 1, link 1 == LDT 1
 260                                 chip southbridge/nvidia/ck804
 261                                         device pci 0.0 on end   # HT
 262                                         device pci 1.0 on end   # LPC
 263                                         device pci 1.1 off end # SM
 264                                         device pci 2.0 off end # USB 1.1
 265                                         device pci 2.1 off end # USB 2
 266                                         device pci 4.0 off end # ACI
 267                                         device pci 4.1 off end # MCI
 268                                         device pci 6.0 off end # IDE
 269                                         device pci 7.0 off end # SATA 1
 270                                         device pci 8.0 off end # SATA 0
 271                                         device pci 9.0 off end # PCI
 272                                         device pci a.0 on end # NIC
 273                                         device pci b.0 off end # PCI E 3
 274                                         device pci c.0 off end # PCI E 2
 275                                         device pci d.0 off end # PCI E 1
 276                                         device pci e.0 on end # PCI E 0
 277 #                                       register "nic_rom_address" = "0xfff80000" # 64k
 278                                         register "mac_eeprom_smbus" = "3"
 279                                         register "mac_eeprom_addr" = "0x51"
 280                                 end
 281                         end #  device pci 19.0
 282
 283                         device pci 19.0 on end
 284                         device pci 19.1 on end
 285                         device pci 19.2 on end
 286                         device pci 19.3 on end
 287                 end
 288         end # PCI domain
 289
 290 end #root_complex