2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The coreboot bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
19 default CONFIG_ROM_PAYLOAD = 1
22 ## Compute where this copy of coreboot will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up coreboot,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
33 default XIP_ROM_SIZE=65536
34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
40 ## Build the objects we have code for in this directory.
44 #needed by irq_tables and mptable and acpi_tables
47 if HAVE_MP_TABLE object mptable.o end
48 if HAVE_PIRQ_TABLE object irq_tables.o end
52 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
53 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
57 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
58 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
59 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
60 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
65 ## Build our 16 bit and 32 bit coreboot entry code
68 mainboardinit cpu/x86/16bit/entry16.inc
69 ldscript /cpu/x86/16bit/entry16.lds
72 mainboardinit cpu/x86/32bit/entry32.inc
75 ldscript /cpu/x86/32bit/entry32.lds
79 ldscript /cpu/amd/car/cache_as_ram.lds
83 ## Build our reset vector (This is where coreboot is entered)
86 mainboardinit cpu/x86/16bit/reset16.inc
87 ldscript /cpu/x86/16bit/reset16.lds
89 mainboardinit cpu/x86/32bit/reset32.inc
90 ldscript /cpu/x86/32bit/reset32.lds
94 ## Include an id string (For safe flashing)
96 mainboardinit southbridge/nvidia/ck804/id.inc
97 ldscript /southbridge/nvidia/ck804/id.lds
100 ## ROMSTRAP table for CK804
102 if USE_FALLBACK_IMAGE
103 mainboardinit southbridge/nvidia/ck804/romstrap.inc
104 ldscript /southbridge/nvidia/ck804/romstrap.lds
108 ## Setup Cache-As-Ram
110 mainboardinit cpu/amd/car/cache_as_ram.inc
113 ### This is the early phase of coreboot startup
114 ### Things are delicate and we test to see if we should
115 ### failover to another image.
117 if USE_FALLBACK_IMAGE
118 ldscript /arch/i386/lib/failover.lds
127 mainboardinit ./auto.inc
131 ## Include the secondary Configuration files
135 # sample config for tyan/s2895
136 chip northbridge/amd/amdk8/root_complex
137 device apic_cluster 0 on
138 chip cpu/amd/socket_940
142 device pci_domain 0 on
143 chip northbridge/amd/amdk8 #mc0
144 device pci 18.0 on end # link 0
145 device pci 18.0 on # link1
146 # devices on link 0, link 0 == LDT 0
147 chip southbridge/nvidia/ck804
148 device pci 0.0 on end # HT
149 device pci 1.0 on # LPC
150 chip superio/smsc/lpc47m10x
151 device pnp 2e.0 off # Floppy
156 device pnp 2e.3 off # Parallel Port
160 device pnp 2e.4 on # Com1
164 device pnp 2e.5 off # Com2
168 device pnp 2e.7 off # Keyboard
176 device pci 1.1 on # SM 0
177 chip drivers/generic/generic #dimm 0-0-0
180 chip drivers/generic/generic #dimm 0-0-1
183 chip drivers/generic/generic #dimm 0-1-0
186 chip drivers/generic/generic #dimm 0-1-1
189 chip drivers/generic/generic #dimm 1-0-0
192 chip drivers/generic/generic #dimm 1-0-1
195 chip drivers/generic/generic #dimm 1-1-0
198 chip drivers/generic/generic #dimm 1-1-1
202 device pci 1.1 on # SM 1
203 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
204 # chip drivers/generic/generic #PCIXA Slot1
205 # device i2c 50 on end
207 # chip drivers/generic/generic #PCIXB Slot1
208 # device i2c 51 on end
210 # chip drivers/generic/generic #PCIXB Slot2
211 # device i2c 52 on end
213 # chip drivers/generic/generic #PCI Slot1
214 # device i2c 53 on end
216 # chip drivers/generic/generic #Master CK804 PCI-E
217 # device i2c 54 on end
219 # chip drivers/generic/generic #Slave CK804 PCI-E
220 # device i2c 55 on end
222 chip drivers/generic/generic #MAC EEPROM
227 device pci 2.0 on end # USB 1.1
228 device pci 2.1 on end # USB 2
229 device pci 4.0 on end # ACI
230 device pci 4.1 off end # MCI
231 device pci 6.0 on end # IDE
232 device pci 7.0 on end # SATA 1
233 device pci 8.0 on end # SATA 0
234 device pci 9.0 on end # PCI
235 device pci a.0 on end # NIC
236 device pci b.0 off end # PCI E 3
237 device pci c.0 off end # PCI E 2
238 device pci d.0 off end # PCI E 1
239 device pci e.0 on end # PCI E 0
240 register "ide0_enable" = "1"
241 register "ide1_enable" = "1"
242 register "sata0_enable" = "1"
243 register "sata1_enable" = "1"
244 # register "nic_rom_address" = "0xfff80000" # 64k
245 # register "raid_rom_address" = "0xfff90000"
246 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
247 register "mac_eeprom_addr" = "0x51"
249 end # device pci 18.0
250 device pci 18.0 on end # link 2
251 device pci 18.1 on end
252 device pci 18.2 on end
253 device pci 18.3 on end
256 chip northbridge/amd/amdk8
257 device pci 19.0 on end # link 0
259 # devices on link 1, link 1 == LDT 1
260 chip southbridge/nvidia/ck804
261 device pci 0.0 on end # HT
262 device pci 1.0 on end # LPC
263 device pci 1.1 off end # SM
264 device pci 2.0 off end # USB 1.1
265 device pci 2.1 off end # USB 2
266 device pci 4.0 off end # ACI
267 device pci 4.1 off end # MCI
268 device pci 6.0 off end # IDE
269 device pci 7.0 off end # SATA 1
270 device pci 8.0 off end # SATA 0
271 device pci 9.0 off end # PCI
272 device pci a.0 on end # NIC
273 device pci b.0 off end # PCI E 3
274 device pci c.0 off end # PCI E 2
275 device pci d.0 off end # PCI E 1
276 device pci e.0 on end # PCI E 0
277 # register "nic_rom_address" = "0xfff80000" # 64k
278 register "mac_eeprom_smbus" = "3"
279 register "mac_eeprom_addr" = "0x51"
281 end # device pci 19.0
283 device pci 19.0 on end
284 device pci 19.1 on end
285 device pci 19.2 on end
286 device pci 19.3 on end