2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
19 default CONFIG_ROM_PAYLOAD = 1
22 ## Compute where this copy of linuxBIOS will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up linuxBIOS,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
33 default XIP_ROM_SIZE=65536
34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
40 ## Build the objects we have code for in this directory.
44 #needed by irq_tables and mptable and acpi_tables
47 if HAVE_MP_TABLE object mptable.o end
48 if HAVE_PIRQ_TABLE object irq_tables.o end
54 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
55 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
59 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
60 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
61 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
62 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
71 depends "$(MAINBOARD)/failover.c ./romcc"
72 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
75 makerule ./failover.inc
76 depends "$(MAINBOARD)/failover.c ./romcc"
77 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
81 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
82 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
86 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
87 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
93 ## Build our 16 bit and 32 bit linuxBIOS entry code
96 mainboardinit cpu/x86/16bit/entry16.inc
97 ldscript /cpu/x86/16bit/entry16.lds
100 mainboardinit cpu/x86/32bit/entry32.inc
104 ldscript /cpu/x86/32bit/entry32.lds
108 ldscript /cpu/amd/car/cache_as_ram.lds
114 ## Build our reset vector (This is where linuxBIOS is entered)
116 if USE_FALLBACK_IMAGE
117 mainboardinit cpu/x86/16bit/reset16.inc
118 ldscript /cpu/x86/16bit/reset16.lds
120 mainboardinit cpu/x86/32bit/reset32.inc
121 ldscript /cpu/x86/32bit/reset32.lds
126 ### Should this be in the northbridge code?
127 mainboardinit arch/i386/lib/cpu_reset.inc
131 ## Include an id string (For safe flashing)
133 mainboardinit southbridge/nvidia/ck804/id.inc
134 ldscript /southbridge/nvidia/ck804/id.lds
137 ## ROMSTRAP table for CK804
139 if USE_FALLBACK_IMAGE
140 mainboardinit southbridge/nvidia/ck804/romstrap.inc
141 ldscript /southbridge/nvidia/ck804/romstrap.lds
148 ## Setup Cache-As-Ram
150 mainboardinit cpu/amd/car/cache_as_ram.inc
154 ### This is the early phase of linuxBIOS startup
155 ### Things are delicate and we test to see if we should
156 ### failover to another image.
158 if USE_FALLBACK_IMAGE
159 ldscript /arch/i386/lib/failover.lds
162 mainboardinit ./failover.inc
174 mainboardinit ./auto.inc
179 mainboardinit cpu/x86/fpu/enable_fpu.inc
180 mainboardinit cpu/x86/mmx/enable_mmx.inc
181 mainboardinit cpu/x86/sse/enable_sse.inc
182 mainboardinit ./auto.inc
183 mainboardinit cpu/x86/sse/disable_sse.inc
184 mainboardinit cpu/x86/mmx/disable_mmx.inc
189 ## Include the secondary Configuration files
195 # sample config for tyan/s2895
196 chip northbridge/amd/amdk8/root_complex
197 device apic_cluster 0 on
198 chip cpu/amd/socket_940
202 device pci_domain 0 on
203 chip northbridge/amd/amdk8 #mc0
204 device pci 18.0 on end # link 0
205 device pci 18.0 on # link1
206 # devices on link 0, link 0 == LDT 0
207 chip southbridge/nvidia/ck804
208 device pci 0.0 on end # HT
209 device pci 1.0 on # LPC
210 chip superio/smsc/lpc47m10x
211 device pnp 2e.0 off # Floppy
216 device pnp 2e.3 off # Parallel Port
220 device pnp 2e.4 on # Com1
224 device pnp 2e.5 off # Com2
228 device pnp 2e.7 off # Keyboard
236 device pci 1.1 on # SM 0
237 chip drivers/generic/generic #dimm 0-0-0
240 chip drivers/generic/generic #dimm 0-0-1
243 chip drivers/generic/generic #dimm 0-1-0
246 chip drivers/generic/generic #dimm 0-1-1
249 chip drivers/generic/generic #dimm 1-0-0
252 chip drivers/generic/generic #dimm 1-0-1
255 chip drivers/generic/generic #dimm 1-1-0
258 chip drivers/generic/generic #dimm 1-1-1
262 device pci 1.1 on # SM 1
263 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
264 # chip drivers/generic/generic #PCIXA Slot1
265 # device i2c 50 on end
267 # chip drivers/generic/generic #PCIXB Slot1
268 # device i2c 51 on end
270 # chip drivers/generic/generic #PCIXB Slot2
271 # device i2c 52 on end
273 # chip drivers/generic/generic #PCI Slot1
274 # device i2c 53 on end
276 # chip drivers/generic/generic #Master CK804 PCI-E
277 # device i2c 54 on end
279 # chip drivers/generic/generic #Slave CK804 PCI-E
280 # device i2c 55 on end
282 chip drivers/generic/generic #MAC EEPROM
287 device pci 2.0 on end # USB 1.1
288 device pci 2.1 on end # USB 2
289 device pci 4.0 on end # ACI
290 device pci 4.1 off end # MCI
291 device pci 6.0 on end # IDE
292 device pci 7.0 on end # SATA 1
293 device pci 8.0 on end # SATA 0
294 device pci 9.0 on end # PCI
295 device pci a.0 on end # NIC
296 device pci b.0 off end # PCI E 3
297 device pci c.0 off end # PCI E 2
298 device pci d.0 off end # PCI E 1
299 device pci e.0 on end # PCI E 0
300 register "ide0_enable" = "1"
301 register "ide1_enable" = "1"
302 register "sata0_enable" = "1"
303 register "sata1_enable" = "1"
304 # register "nic_rom_address" = "0xfff80000" # 64k
305 # register "raid_rom_address" = "0xfff90000"
306 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
307 register "mac_eeprom_addr" = "0x51"
309 end # device pci 18.0
310 device pci 18.0 on end # link 2
311 device pci 18.1 on end
312 device pci 18.2 on end
313 device pci 18.3 on end
316 chip northbridge/amd/amdk8
317 device pci 19.0 on end # link 0
319 # devices on link 1, link 1 == LDT 1
320 chip southbridge/nvidia/ck804
321 device pci 0.0 on end # HT
322 device pci 1.0 on end # LPC
323 device pci 1.1 off end # SM
324 device pci 2.0 off end # USB 1.1
325 device pci 2.1 off end # USB 2
326 device pci 4.0 off end # ACI
327 device pci 4.1 off end # MCI
328 device pci 6.0 off end # IDE
329 device pci 7.0 off end # SATA 1
330 device pci 8.0 off end # SATA 0
331 device pci 9.0 off end # PCI
332 device pci a.0 on end # NIC
333 device pci b.0 off end # PCI E 3
334 device pci c.0 off end # PCI E 2
335 device pci d.0 off end # PCI E 1
336 device pci e.0 on end # PCI E 0
337 # register "nic_rom_address" = "0xfff80000" # 64k
338 register "mac_eeprom_smbus" = "3"
339 register "mac_eeprom_addr" = "0x51"
341 end # device pci 19.0
343 device pci 19.0 on end
344 device pci 19.1 on end
345 device pci 19.2 on end
346 device pci 19.3 on end