2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #include <device/pci_def.h>
27 #include <device/pnp_def.h>
28 #include <arch/romcc_io.h>
30 #include "pc80/serial.c"
31 #include "pc80/udelay_io.c"
32 #include "arch/i386/lib/console.c"
33 #include "ram/ramtest.c"
34 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
35 #include "northbridge/intel/i82830/raminit.h"
36 #include "southbridge/intel/i82801xx/i82801xx.h"
37 #include "cpu/x86/mtrr/earlymtrr.c"
38 #include "cpu/x86/bist.h"
39 #include "spd_table.h"
42 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
44 #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
45 #include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"
48 * The onboard 128MB PC133 memory does not have a SPD EEPROM so the
49 * values have to be set manually, the SO-DIMM socket is located in
50 * socket0 (0x50), and the onboard memory is located in socket1 (0x51).
52 static inline int spd_read_byte(unsigned device, unsigned address)
57 return smbus_read_byte(device, address);
58 } else if (device == 0x51) {
59 for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
60 if (spd_table[i].address == address)
61 return spd_table[i].data;
63 return 0xFF; /* Return 0xFF when address is not found. */
65 return 0xFF; /* Return 0xFF on any failures. */
69 #include "northbridge/intel/i82830/raminit.c"
70 #include "sdram/generic_sdram.c"
73 * The AC'97 Audio Controller I/O space registers are read only by default
74 * so we need to enable them by setting register 0x41 to 0x01.
76 static void ac97_io_enable(void)
80 /* Set the ac97 audio device staticly. */
81 dev = PCI_DEV(0x0, 0x1f, 0x5);
83 /* Enable access to the IO space. */
84 pci_write_config8(dev, 0x41, 0x01);
87 static void main(unsigned long bist)
89 static const struct mem_controller memctrl[] = {
91 .d0 = PCI_DEV(0, 0, 0),
92 .channel0 = {0x50, 0x51},
101 smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE);
106 /* Halt if there was a built in self test failure. */
107 report_bist_failure(bist);
109 sdram_set_registers(memctrl);
110 sdram_set_spd_registers(memctrl);
111 sdram_enable(0, memctrl);
114 /* ram_check(0, 640 * 1024); */
115 /* ram_check(130048 * 1024, 131072 * 1024); */
117 i82801xx_halt_tco_timer();