2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 include /config/nofailovercalculation.lb
25 if HAVE_PIRQ_TABLE object irq_tables.o end
33 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
34 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
36 makerule ./failover.inc
37 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
38 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
41 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
42 depends "$(MAINBOARD)/auto.c ../romcc"
43 action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
46 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
47 depends "$(MAINBOARD)/auto.c ../romcc"
48 action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
50 mainboardinit cpu/x86/16bit/entry16.inc
51 mainboardinit cpu/x86/32bit/entry32.inc
52 ldscript /cpu/x86/16bit/entry16.lds
53 ldscript /cpu/x86/32bit/entry32.lds
55 mainboardinit cpu/x86/16bit/reset16.inc
56 ldscript /cpu/x86/16bit/reset16.lds
58 mainboardinit cpu/x86/32bit/reset32.inc
59 ldscript /cpu/x86/32bit/reset32.lds
61 mainboardinit arch/i386/lib/cpu_reset.inc
62 mainboardinit arch/i386/lib/id.inc
63 ldscript /arch/i386/lib/id.lds
65 ldscript /arch/i386/lib/failover.lds
66 mainboardinit ./failover.inc
68 mainboardinit cpu/x86/fpu/enable_fpu.inc
69 mainboardinit cpu/x86/mmx/enable_mmx.inc
70 mainboardinit ./auto.inc
71 mainboardinit cpu/x86/mmx/disable_mmx.inc
75 chip northbridge/intel/i82830 # Northbridge
76 device pci_domain 0 on # PCI domain
77 device pci 0.0 on end # Host bridge
78 chip drivers/pci/onboard # Onboard VGA
79 device pci 2.0 on end # VGA (Intel 82830 CGC)
80 register "rom_address" = "0xfff00000"
82 chip southbridge/intel/i82801xx # Southbridge
83 register "pirqa_routing" = "0x05"
84 register "pirqb_routing" = "0x06"
85 register "pirqc_routing" = "0x07"
86 register "pirqd_routing" = "0x09"
87 register "pirqe_routing" = "0x0a"
88 register "pirqf_routing" = "0x80"
89 register "pirqg_routing" = "0x80"
90 register "pirqh_routing" = "0x0b"
92 device pci 1d.0 on end # USB UHCI Controller #1
93 device pci 1d.1 on end # USB UHCI Controller #2
94 device pci 1d.2 on end # USB UHCI Controller #3
95 device pci 1d.7 on end # USB2 EHCI Controller
96 device pci 1e.0 on # PCI bridge
97 device pci 08.0 on end # Intel 82801DB PRO/100 VE Ethernet
99 device pci 1f.0 on # ISA/LPC bridge
100 chip superio/smsc/smscsuperio # Super I/O
101 device pnp 2e.0 off # Floppy
106 device pnp 2e.3 on # Parallel port
111 device pnp 2e.4 on # Com1
115 device pnp 2e.5 on # Com2 / IR
119 device pnp 2e.7 on # PS/2 keyboard/mouse
122 irq 0x70 = 1 # Keyboard interrupt
123 irq 0x72 = 12 # Mouse interrupt
125 device pnp 2e.9 off end # Game port
126 device pnp 2e.a on # PME
129 device pnp 2e.b off end # MPU-401
132 device pci 1f.1 on end # IDE
133 device pci 1f.3 on end # SMBus
134 device pci 1f.5 on end # AC'97 audio
135 device pci 1f.6 on end # AC'97 modem
138 device apic_cluster 0 on # APIC cluster
139 chip cpu/intel/socket_PGA370 # Mobile Celeron Micro-FCBGA Socket 479
140 device apic 0 on end # APIC