2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
6 #include <console/console.h>
7 #include "lib/ramtest.c"
8 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
9 #include "cpu/x86/bist.h"
10 #include "cpu/x86/msr.h"
11 #include <cpu/amd/gx2def.h>
12 #include <cpu/amd/geode_post_code.h>
14 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
16 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
17 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
19 static inline int spd_read_byte(unsigned device, unsigned address)
21 return smbus_read_byte(device, address);
24 #include "northbridge/amd/gx2/raminit.h"
26 static inline unsigned int fls(unsigned int x)
30 __asm__("bsfl %1,%0\n\t"
33 "1:" : "=r" (r) : "g" (x));
37 /* sdram parameters for OLPC:
42 d0_MB=1 (module banks)
43 d0_cb=4 (component banks)
44 do_psz=4KB (page size)
45 Trc=10 (clocks) (ref2act)
52 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
54 /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
55 * component Banks (byte 17) * module banks, side (byte 5) *
56 * width in bits (byte 6,7)
57 * = Density per side (byte 31) * number of sides (byte 5) */
58 /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
60 unsigned char module_banks, val;
62 msr = rdmsr(MC_CF07_DATA);
64 /* get module banks (sides) per dimm, SPD byte 5 */
67 msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
68 msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
70 /* get component banks per module bank, SPD byte 17 */
73 msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
74 msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
76 /* get the module bank density, SPD byte 31 */
77 /* this is multiples of 8 MB */
78 /* actually it is 2^x*4, where x is the value you put in */
79 /* for OLPC, set default size */
80 /* dimm size - hardcoded 128Mb */
82 msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
83 msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
85 /* page size = 2^col address */
86 val = 2; /* 4096 bytes */
87 msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
88 msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
90 print_debug("computed msr.hi ");
91 print_debug_hex32(msr.hi);
94 /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
95 /* well, it may be close. It's about 200,000 ticks */
97 wrmsr(MC_CF07_DATA, msr);
99 /* timing and mode ... */
101 msr = rdmsr(0x20000019);
103 /* per standard bios settings */
116 /* the msr value reported by quanta is very, very different.
117 * we will go with that value for now.
121 wrmsr(0x20000019, msr);
125 #include "northbridge/amd/gx2/raminit.c"
126 #include "lib/generic_sdram.c"
128 #define PLLMSRhi 0x00001490
129 #define PLLMSRlo 0x02000030
130 #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
131 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
132 #include "northbridge/amd/gx2/pll_reset.c"
133 #include "cpu/amd/model_gx2/cpureginit.c"
134 #include "cpu/amd/model_gx2/syspreinit.c"
135 #include "cpu/amd/model_lx/msrinit.c"
137 static void gpio_init(void)
141 /* Make sure events enable for gpio 12 is off */
143 m = inl(GPIOL_EVENTS_ENABLE);
146 outl(m, GPIOL_EVENTS_ENABLE);
149 void main(unsigned long bist)
151 static const struct mem_controller memctrl [] = {
152 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
158 cs5536_early_setup();
160 /* NOTE: must do this AFTER the early_setup!
161 * it is counting on some early MSR setup
164 cs5536_setup_onchipuart(1);
169 /* Halt if there was a built in self test failure */
170 report_bist_failure(bist);
175 print_err("done cpuRegInit\n");
177 sdram_initialize(1, memctrl);
179 /* Check all of memory */
180 //ram_check(0x00000000, 640*1024);