5 #include <device/pci_def.h>
7 #include <device/pnp_def.h>
8 #include <arch/romcc_io.h>
10 #include "pc80/serial.c"
11 #include "arch/i386/lib/console.c"
12 #include "lib/ramtest.c"
13 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
14 #include "cpu/x86/bist.h"
15 #include "cpu/x86/msr.h"
16 #include <cpu/amd/gx2def.h>
18 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
20 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
21 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
23 static inline int spd_read_byte(unsigned device, unsigned address)
25 return smbus_read_byte(device, address);
28 #include "northbridge/amd/gx2/raminit.h"
30 static inline unsigned int fls(unsigned int x)
34 __asm__("bsfl %1,%0\n\t"
37 "1:" : "=r" (r) : "g" (x));
44 /* sdram parameters for OLPC:
49 d0_MB=1 (module banks)
50 d0_cb=4 (component banks)
51 do_psz=4KB (page size)
52 Trc=10 (clocks) (ref2act)
59 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
61 /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
62 * component Banks (byte 17) * module banks, side (byte 5) *
63 * width in bits (byte 6,7)
64 * = Density per side (byte 31) * number of sides (byte 5) */
65 /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
67 unsigned char module_banks, val;
69 msr = rdmsr(MC_CF07_DATA);
71 /* get module banks (sides) per dimm, SPD byte 5 */
74 msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
75 msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
77 /* get component banks per module bank, SPD byte 17 */
80 msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
81 msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
83 /* get the module bank density, SPD byte 31 */
84 /* this is multiples of 8 MB */
85 /* actually it is 2^x*4, where x is the value you put in */
86 /* for OLPC, set default size */
87 /* dimm size - hardcoded 128Mb */
89 msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
90 msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
92 /* page size = 2^col address */
93 val = 2; /* 4096 bytes */
94 msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
95 msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
97 print_debug("computed msr.hi ");
98 print_debug_hex32(msr.hi);
101 /* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
102 /* well, it may be close. It's about 200,000 ticks */
104 wrmsr(MC_CF07_DATA, msr);
106 /* timing and mode ... */
108 msr = rdmsr(0x20000019);
110 /* per standard bios settings */
123 /* the msr value reported by quanta is very, very different.
124 * we will go with that value for now.
128 wrmsr(0x20000019, msr);
132 #include "northbridge/amd/gx2/raminit.c"
133 #include "lib/generic_sdram.c"
135 #define PLLMSRhi 0x00001490
136 #define PLLMSRlo 0x02000030
137 #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
138 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
139 #include "northbridge/amd/gx2/pll_reset.c"
140 #include "cpu/amd/model_gx2/cpureginit.c"
141 #include "cpu/amd/model_gx2/syspreinit.c"
142 static void msr_init(void)
144 __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
146 __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
147 __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
149 __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
150 __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
153 static void gpio_init(void)
157 /* Make sure events enable for gpio 12 is off */
159 m = inl(GPIOL_EVENTS_ENABLE);
162 outl(m, GPIOL_EVENTS_ENABLE);
165 static void main(unsigned long bist)
167 static const struct mem_controller memctrl [] = {
168 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
174 cs5536_early_setup();
176 /* NOTE: must do this AFTER the early_setup!
177 * it is counting on some early MSR setup
180 cs5536_setup_onchipuart();
188 print_err("done cpuRegInit\n");
190 sdram_initialize(1, memctrl);
192 /* Check all of memory */
193 //ram_check(0x00000000, 640*1024);