1 uses CONFIG_GENERATE_MP_TABLE
2 uses CONFIG_GENERATE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_HAVE_OPTION_TABLE
7 uses CONFIG_USE_OPTION_TABLE
8 uses CONFIG_ROM_PAYLOAD
9 uses CONFIG_IRQ_SLOT_COUNT
11 uses CONFIG_MAINBOARD_VENDOR
12 uses CONFIG_MAINBOARD_PART_NUMBER
13 uses COREBOOT_EXTRA_VERSION
15 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_STACK_SIZE
19 uses CONFIG_ROM_SECTION_SIZE
20 uses CONFIG_ROM_IMAGE_SIZE
21 uses CONFIG_ROM_SECTION_SIZE
22 uses CONFIG_ROM_SECTION_OFFSET
23 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
25 uses CONFIG_PRECOMPRESSED_PAYLOAD
28 uses CONFIG_XIP_ROM_SIZE
29 uses CONFIG_XIP_ROM_BASE
30 uses CONFIG_GENERATE_MP_TABLE
31 uses CONFIG_CROSS_COMPILE
35 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
36 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
37 uses CONFIG_CONSOLE_SERIAL8250
38 uses CONFIG_TTYS0_BAUD
39 uses CONFIG_TTYS0_BASE
41 uses CONFIG_UDELAY_TSC
42 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
44 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
45 default CONFIG_ROM_SIZE = 256*1024
52 ## Build code for the fallback boot
54 default CONFIG_HAVE_FALLBACK_BOOT=1
59 default CONFIG_GENERATE_MP_TABLE=0
62 ## Build code to reset the motherboard from coreboot
64 default CONFIG_HAVE_HARD_RESET=0
66 ## Delay timer options
68 default CONFIG_UDELAY_TSC=1
69 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
72 ## Build code to export a programmable irq routing table
74 default CONFIG_GENERATE_PIRQ_TABLE=1
75 default CONFIG_IRQ_SLOT_COUNT=2
79 ## Build code to export a CMOS option table
81 default CONFIG_HAVE_OPTION_TABLE=0
84 ### coreboot layout values
87 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
88 default CONFIG_ROM_IMAGE_SIZE = 65536
89 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
92 ## Use a small 8K stack
94 default CONFIG_STACK_SIZE=0x2000
97 ## Use a small 16K heap
99 default CONFIG_HEAP_SIZE=0x4000
102 ## Only use the option table in a normal image
104 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
105 default CONFIG_USE_OPTION_TABLE = 0
107 default CONFIG_RAMBASE = 0x00004000
109 default CONFIG_ROM_PAYLOAD = 1
112 ## The default compiler
114 default CONFIG_CROSS_COMPILE=""
115 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
119 ## The Serial Console
122 # To Enable the Serial Console
123 default CONFIG_CONSOLE_SERIAL8250=1
125 ## Select the serial console baud rate
126 default CONFIG_TTYS0_BAUD=115200
127 #default CONFIG_TTYS0_BAUD=57600
128 #default CONFIG_TTYS0_BAUD=38400
129 #default CONFIG_TTYS0_BAUD=19200
130 #default CONFIG_TTYS0_BAUD=9600
131 #default CONFIG_TTYS0_BAUD=4800
132 #default CONFIG_TTYS0_BAUD=2400
133 #default CONFIG_TTYS0_BAUD=1200
135 # Select the serial console base port
136 default CONFIG_TTYS0_BASE=0x3f8
138 # Select the serial protocol
139 # This defaults to 8 data bits, 1 stop bit, and no parity
140 default CONFIG_TTYS0_LCS=0x3
143 ### Select the coreboot loglevel
145 ## EMERG 1 system is unusable
146 ## ALERT 2 action must be taken immediately
147 ## CRIT 3 critical conditions
148 ## ERR 4 error conditions
149 ## WARNING 5 warning conditions
150 ## NOTICE 6 normal but significant condition
151 ## INFO 7 informational
152 ## CONFIG_DEBUG 8 debug-level messages
153 ## SPEW 9 Way too many details
155 ## Request this level of debugging output
156 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
157 ## At a maximum only compile in this level of debugging
158 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8