2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define RAMINIT_SYSINFO 1
24 #define K8_ALLOCATE_IO_RANGE 1
26 #define QRANK_DIMM_SUPPORT 1
28 #if CONFIG_LOGICAL_CPUS==1
29 #define SET_NB_CFG_54 1
32 //used by init_cpus and fidvid
34 //if we want to wait for core1 done before DQS training, set it to 0
35 #define SET_FIDVID_CORE0_ONLY 1
37 #if CONFIG_K8_REV_F_SUPPORT == 1
38 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
41 #define DBGP_DEFAULT 7
45 #include <device/pci_def.h>
46 #include <device/pci_ids.h>
48 #include <device/pnp_def.h>
49 #include <arch/romcc_io.h>
50 #include <cpu/x86/lapic.h>
51 #include "option_table.h"
52 #include "pc80/mc146818rtc_early.c"
54 #include "pc80/serial.c"
55 #include "console/console.c"
56 #if CONFIG_USBDEBUG_DIRECT
57 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
58 #include "pc80/usbdebug_direct_serial.c"
60 #include "lib/ramtest.c"
62 #include <cpu/amd/model_fxx_rev.h>
64 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
65 #include "northbridge/amd/amdk8/raminit.h"
66 #include "cpu/amd/model_fxx/apic_timer.c"
67 #include "lib/delay.c"
69 #include "cpu/x86/lapic/boot_cpu.c"
70 #include "northbridge/amd/amdk8/reset_test.c"
71 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
72 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
74 #include "cpu/x86/bist.h"
76 #include "northbridge/amd/amdk8/debug.c"
78 #include "cpu/x86/mtrr/earlymtrr.c"
80 #include "northbridge/amd/amdk8/setup_resource_map.c"
82 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
84 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
86 static void memreset(int controllers, const struct mem_controller *ctrl)
90 static inline void activate_spd_rom(const struct mem_controller *ctrl)
95 static inline int spd_read_byte(unsigned device, unsigned address)
97 return smbus_read_byte(device, address);
100 #include "northbridge/amd/amdk8/amdk8_f.h"
101 #include "northbridge/amd/amdk8/incoherent_ht.c"
102 #include "northbridge/amd/amdk8/coherent_ht.c"
103 #include "northbridge/amd/amdk8/raminit_f.c"
104 #include "lib/generic_sdram.c"
106 #include "resourcemap.c"
108 #include "cpu/amd/dualcore/dualcore.c"
111 #define MCP55_USE_NIC 1
112 #define MCP55_USE_AZA 1
114 #define MCP55_PCI_E_X_0 2
115 #define MCP55_PCI_E_X_1 4
117 #define MCP55_MB_SETUP \
118 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
119 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
120 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
121 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
122 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
123 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
125 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
126 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
130 #include "cpu/amd/car/post_cache_as_ram.c"
132 #include "cpu/amd/model_fxx/init_cpus.c"
134 #include "cpu/amd/model_fxx/fidvid.c"
136 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
137 #include "northbridge/amd/amdk8/early_ht.c"
139 static void sio_setup(void)
144 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
146 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
148 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
150 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
152 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
154 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
157 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
159 static const uint16_t spd_addr [] = {
161 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
162 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
164 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
165 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
168 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
169 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
172 unsigned bsp_apicid = 0;
174 if (!cpu_init_detectedx && boot_cpu()) {
175 /* Nothing special needs to be done to find bus 0 */
176 /* Allow the HT devices to be found */
178 enumerate_ht_chain();
182 /* Setup the mcp55 */
187 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
190 pnp_enter_ext_func_mode(SERIAL_DEV);
191 pnp_write_config(SERIAL_DEV, 0x24, 0);
192 w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
193 pnp_exit_ext_func_mode(SERIAL_DEV);
195 setup_mb_resource_map();
199 /* Halt if there was a built in self test failure */
200 report_bist_failure(bist);
202 #if CONFIG_USBDEBUG_DIRECT
203 mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
204 early_usbdebug_direct_init();
207 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
209 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
211 #if CONFIG_MEM_TRAIN_SEQ == 1
212 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
214 setup_coherent_ht_domain(); // routing table and start other core0
216 wait_all_core0_started();
217 #if CONFIG_LOGICAL_CPUS==1
218 // It is said that we should start core1 after all core0 launched
219 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
220 * So here need to make sure last core0 is started, esp for two way system,
221 * (there may be apic id conflicts in that case)
224 wait_all_other_cores_started(bsp_apicid);
227 /* it will set up chains and store link pair for optimization later */
228 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
234 msr=rdmsr(0xc0010042);
235 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
241 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
243 init_fidvid_bsp(bsp_apicid);
245 // show final fid and vid
248 msr=rdmsr(0xc0010042);
249 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
254 needs_reset |= optimize_link_coherent_ht();
255 needs_reset |= optimize_link_incoherent_ht(sysinfo);
256 needs_reset |= mcp55_early_setup_x();
258 // fidvid change will issue one LDTSTOP and the HT change will be effective too
260 print_info("ht reset -\n");
263 allow_all_aps_stop(bsp_apicid);
265 //It's the time to set ctrl in sysinfo now;
266 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
270 //do we need apci timer, tsc...., only debug need it for better output
271 /* all ap stopped? */
272 // init_timer(); // Need to use TMICT to synconize FID/VID
274 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
276 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now