2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define RAMINIT_SYSINFO 1
27 #define K8_ALLOCATE_IO_RANGE 1
29 #define QRANK_DIMM_SUPPORT 1
31 #if CONFIG_LOGICAL_CPUS==1
32 #define SET_NB_CFG_54 1
35 //used by init_cpus and fidvid
36 #define K8_SET_FIDVID 0
37 //if we want to wait for core1 done before DQS training, set it to 0
38 #define K8_SET_FIDVID_CORE0_ONLY 1
40 #if CONFIG_K8_REV_F_SUPPORT == 1
41 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
44 #define DBGP_DEFAULT 7
48 #include <device/pci_def.h>
49 #include <device/pci_ids.h>
51 #include <device/pnp_def.h>
52 #include <arch/romcc_io.h>
53 #include <cpu/x86/lapic.h>
54 #include "option_table.h"
55 #include "pc80/mc146818rtc_early.c"
57 #if CONFIG_USE_FAILOVER_IMAGE==0
58 #include "pc80/serial.c"
59 #include "arch/i386/lib/console.c"
60 #if CONFIG_USBDEBUG_DIRECT
61 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
62 #include "pc80/usbdebug_direct_serial.c"
64 #include "lib/ramtest.c"
66 #include <cpu/amd/model_fxx_rev.h>
68 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
69 #include "northbridge/amd/amdk8/raminit.h"
70 #include "cpu/amd/model_fxx/apic_timer.c"
71 #include "lib/delay.c"
75 #include "cpu/x86/lapic/boot_cpu.c"
76 #include "northbridge/amd/amdk8/reset_test.c"
77 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
78 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
80 #if CONFIG_USE_FAILOVER_IMAGE==0
82 #include "cpu/x86/bist.h"
84 #include "northbridge/amd/amdk8/debug.c"
86 #include "cpu/amd/mtrr/amd_earlymtrr.c"
88 #include "northbridge/amd/amdk8/setup_resource_map.c"
90 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
92 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
94 static void memreset_setup(void)
98 static void memreset(int controllers, const struct mem_controller *ctrl)
102 static inline void activate_spd_rom(const struct mem_controller *ctrl)
107 static inline int spd_read_byte(unsigned device, unsigned address)
109 return smbus_read_byte(device, address);
112 #include "northbridge/amd/amdk8/amdk8_f.h"
113 #include "northbridge/amd/amdk8/coherent_ht.c"
115 #include "northbridge/amd/amdk8/incoherent_ht.c"
117 #include "northbridge/amd/amdk8/raminit_f.c"
119 #include "lib/generic_sdram.c"
121 #include "resourcemap.c"
123 #include "cpu/amd/dualcore/dualcore.c"
126 #define MCP55_USE_NIC 1
127 #define MCP55_USE_AZA 1
129 #define MCP55_PCI_E_X_0 2
130 #define MCP55_PCI_E_X_1 4
132 #define MCP55_MB_SETUP \
133 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
134 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
135 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
136 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
137 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
138 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
140 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
141 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
143 #include "cpu/amd/car/copy_and_run.c"
145 #include "cpu/amd/car/post_cache_as_ram.c"
147 #include "cpu/amd/model_fxx/init_cpus.c"
149 #include "cpu/amd/model_fxx/fidvid.c"
153 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
155 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
156 #include "northbridge/amd/amdk8/early_ht.c"
159 static void sio_setup(void)
166 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
168 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
170 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
172 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
174 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
176 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
180 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
182 unsigned last_boot_normal_x = last_boot_normal();
184 /* Is this a cpu only reset? or Is this a secondary cpu? */
185 if ((cpu_init_detectedx) || (!boot_cpu())) {
186 if (last_boot_normal_x) {
193 /* Nothing special needs to be done to find bus 0 */
194 /* Allow the HT devices to be found */
196 enumerate_ht_chain();
200 /* Setup the mcp55 */
203 /* Is this a deliberate reset by the bios */
204 if (bios_reset_detected() && last_boot_normal_x) {
207 /* This is the primary cpu how should I boot? */
208 else if (do_normal_boot()) {
215 __asm__ volatile ("jmp __normal_image"
217 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
221 #if CONFIG_HAVE_FAILOVER_BOOT==1
222 __asm__ volatile ("jmp __fallback_image"
224 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
230 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
232 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
234 #if CONFIG_HAVE_FAILOVER_BOOT==1
235 #if CONFIG_USE_FAILOVER_IMAGE==1
236 failover_process(bist, cpu_init_detectedx);
238 real_main(bist, cpu_init_detectedx);
241 #if CONFIG_USE_FALLBACK_IMAGE == 1
242 failover_process(bist, cpu_init_detectedx);
244 real_main(bist, cpu_init_detectedx);
248 #if CONFIG_USE_FAILOVER_IMAGE==0
250 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
252 static const uint16_t spd_addr [] = {
253 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
254 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
255 #if CONFIG_MAX_PHYSICAL_CPUS > 1
256 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
257 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
261 struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
264 unsigned bsp_apicid = 0;
267 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
270 pnp_enter_ext_func_mode(SERIAL_DEV);
271 pnp_write_config(SERIAL_DEV, 0x24, 0);
272 w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
273 pnp_exit_ext_func_mode(SERIAL_DEV);
275 setup_mb_resource_map();
279 /* Halt if there was a built in self test failure */
280 report_bist_failure(bist);
283 #if CONFIG_USBDEBUG_DIRECT
284 mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
285 early_usbdebug_direct_init();
288 print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
290 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
292 #if CONFIG_MEM_TRAIN_SEQ == 1
293 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
295 setup_coherent_ht_domain(); // routing table and start other core0
297 wait_all_core0_started();
298 #if CONFIG_LOGICAL_CPUS==1
299 // It is said that we should start core1 after all core0 launched
300 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
301 * So here need to make sure last core0 is started, esp for two way system,
302 * (there may be apic id conflicts in that case)
305 wait_all_other_cores_started(bsp_apicid);
308 /* it will set up chains and store link pair for optimization later */
309 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
311 #if K8_SET_FIDVID == 1
315 msr=rdmsr(0xc0010042);
316 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
322 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
324 init_fidvid_bsp(bsp_apicid);
326 // show final fid and vid
329 msr=rdmsr(0xc0010042);
330 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
335 needs_reset |= optimize_link_coherent_ht();
336 needs_reset |= optimize_link_incoherent_ht(sysinfo);
337 needs_reset |= mcp55_early_setup_x();
339 // fidvid change will issue one LDTSTOP and the HT change will be effective too
341 print_info("ht reset -\r\n");
344 allow_all_aps_stop(bsp_apicid);
346 //It's the time to set ctrl in sysinfo now;
347 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
353 //do we need apci timer, tsc...., only debug need it for better output
354 /* all ap stopped? */
355 // init_timer(); // Need to use TMICT to synconize FID/VID
357 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
359 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now