src/mainboard/nvidia/l1_2pvv/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ##
  23 ## Compute the location and size of where this firmware image
  24 ## (coreboot plus bootloader) will live in the boot rom chip.
  25 ##
  26 if USE_FAILOVER_IMAGE
  27         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  28         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  29 else
  30     if USE_FALLBACK_IMAGE
  31         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  32         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  33     else
  34         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35         default ROM_SECTION_OFFSET = 0
  36     end
  37 end
  38
  39 ##
  40 ## Compute the start location and size size of
  41 ## The coreboot bootloader.
  42 ##
  43 default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  45
  46 ##
  47 ## Compute where this copy of coreboot will start in the boot rom
  48 ##
  49 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  50
  51 ##
  52 ## Compute a range of ROM that can cached to speed up coreboot,
  53 ## execution speed.
  54 ##
  55 ## XIP_ROM_SIZE must be a power of 2.
  56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  57 ##
  58 default XIP_ROM_SIZE=65536
  59
  60 if USE_FAILOVER_IMAGE
  61         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  62 else
  63     if USE_FALLBACK_IMAGE
  64         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  65     else
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  67     end
  68 end
  69
  70 arch i386 end
  71
  72 ##
  73 ## Build the objects we have code for in this directory.
  74 ##
  75
  76 driver mainboard.o
  77 #needed by irq_tables and mptable and acpi_tables
  78 object get_bus_conf.o
  79
  80 if HAVE_MP_TABLE object mptable.o end
  81 if HAVE_PIRQ_TABLE object irq_tables.o end
  82 #object reset.o
  83
  84 if HAVE_ACPI_TABLES
  85         object acpi_tables.o
  86         object fadt.o
  87         makerule dsdt.c
  88                 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
  89                 action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
  90                 action  "mv dsdt_lb.hex dsdt.c"
  91         end
  92         object ./dsdt.o
  93
  94         #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
  95
  96         if ACPI_SSDTX_NUM
  97             makerule ssdt6.c
  98                         depends "$(MAINBOARD)/dx/pci6.asl"
  99                         action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
 100                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
 101                         action  "mv pci6.hex ssdt6.c"
 102             end
 103             object ./ssdt6.o
 104             makerule ssdt5.c
 105                         depends "$(MAINBOARD)/dx/pci5.asl"
 106                         action  "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
 107                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
 108                         action  "mv pci5.hex ssdt5.c"
 109             end
 110             object ./ssdt5.o
 111         end
 112 end
 113
 114         if CONFIG_USE_INIT
 115                 makerule ./cache_as_ram_auto.o
 116                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 117                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
 118                 end
 119         else
 120                 makerule ./cache_as_ram_auto.inc
 121                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 122                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
 123                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
 124                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
 125                 end
 126         end
 127
 128 if USE_FAILOVER_IMAGE
 129 else
 130     if CONFIG_AP_CODE_IN_CAR
 131         makerule ./apc_auto.o
 132                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 133                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
 134         end
 135         ldscript /arch/i386/init/ldscript_apc.lb
 136     end
 137 end
 138
 139
 140 ##
 141 ## Build our 16 bit and 32 bit coreboot entry code
 142 ##
 143 if HAVE_FAILOVER_BOOT
 144     if USE_FAILOVER_IMAGE
 145         mainboardinit cpu/x86/16bit/entry16.inc
 146         ldscript /cpu/x86/16bit/entry16.lds
 147     end
 148 else
 149     if USE_FALLBACK_IMAGE
 150         mainboardinit cpu/x86/16bit/entry16.inc
 151         ldscript /cpu/x86/16bit/entry16.lds
 152     end
 153 end
 154
 155 mainboardinit cpu/x86/32bit/entry32.inc
 156
 157         if CONFIG_USE_INIT
 158                 ldscript /cpu/x86/32bit/entry32.lds
 159         end
 160
 161         if CONFIG_USE_INIT
 162                 ldscript /cpu/amd/car/cache_as_ram.lds
 163         end
 164
 165 ##
 166 ## Build our reset vector (This is where coreboot is entered)
 167 ##
 168 if HAVE_FAILOVER_BOOT
 169     if USE_FAILOVER_IMAGE
 170         mainboardinit cpu/x86/16bit/reset16.inc
 171         ldscript /cpu/x86/16bit/reset16.lds
 172     else
 173         mainboardinit cpu/x86/32bit/reset32.inc
 174         ldscript /cpu/x86/32bit/reset32.lds
 175     end
 176 else
 177     if USE_FALLBACK_IMAGE
 178         mainboardinit cpu/x86/16bit/reset16.inc
 179         ldscript /cpu/x86/16bit/reset16.lds
 180     else
 181         mainboardinit cpu/x86/32bit/reset32.inc
 182         ldscript /cpu/x86/32bit/reset32.lds
 183     end
 184 end
 185
 186 ##
 187 ## Include an id string (For safe flashing)
 188 ##
 189 mainboardinit southbridge/nvidia/mcp55/id.inc
 190 ldscript /southbridge/nvidia/mcp55/id.lds
 191
 192 ##
 193 ## ROMSTRAP table for MCP55
 194 ##
 195 if HAVE_FAILOVER_BOOT
 196     if USE_FAILOVER_IMAGE
 197         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 198         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 199     end
 200 else
 201     if USE_FALLBACK_IMAGE
 202         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 203         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 204     end
 205 end
 206
 207         ##
 208         ## Setup Cache-As-Ram
 209         ##
 210         mainboardinit cpu/amd/car/cache_as_ram.inc
 211
 212 ###
 213 ### This is the early phase of coreboot startup
 214 ### Things are delicate and we test to see if we should
 215 ### failover to another image.
 216 ###
 217 if HAVE_FAILOVER_BOOT
 218     if USE_FAILOVER_IMAGE
 219                 ldscript /arch/i386/lib/failover_failover.lds
 220     end
 221 else
 222     if USE_FALLBACK_IMAGE
 223                 ldscript /arch/i386/lib/failover.lds
 224     end
 225 end
 226
 227 ##
 228 ## Setup RAM
 229 ##
 230         if CONFIG_USE_INIT
 231                 initobject cache_as_ram_auto.o
 232         else
 233                 mainboardinit ./cache_as_ram_auto.inc
 234         end
 235
 236 ##
 237 ## Include the secondary Configuration files
 238 ##
 239 config chip.h
 240
 241 chip northbridge/amd/amdk8/root_complex
 242         device apic_cluster 0 on
 243                 chip cpu/amd/socket_F
 244                         device apic 0 on end
 245                 end
 246         end
 247         device pci_domain 0 on
 248                 chip northbridge/amd/amdk8 #mc0
 249                         device pci 18.0 on
 250                                 #  devices on link 0, link 0 == LDT 0
 251                                 chip southbridge/nvidia/mcp55
 252                                         device pci 0.0 on end   # HT
 253                                         device pci 1.0 on # LPC
 254                                                 chip superio/winbond/w83627ehg
 255                                                         device pnp 2e.0 off #  Floppy
 256                                                                 io 0x60 = 0x3f0
 257                                                                 irq 0x70 = 6
 258                                                                 drq 0x74 = 2
 259                                                         end
 260                                                         device pnp 2e.1 off #  Parallel Port
 261                                                                 io 0x60 = 0x378
 262                                                                 irq 0x70 = 7
 263                                                         end
 264                                                         device pnp 2e.2 on #  Com1
 265                                                                 io 0x60 = 0x3f8
 266                                                                 irq 0x70 = 4
 267                                                         end
 268                                                         device pnp 2e.3 off #  Com2
 269                                                                 io 0x60 = 0x2f8
 270                                                                 irq 0x70 = 3
 271                                                         end
 272                                                         device pnp 2e.5 on #  Keyboard
 273                                                                 io 0x60 = 0x60
 274                                                                 io 0x62 = 0x64
 275                                                                 irq 0x70 = 1
 276                                                                 irq 0x72 = 12
 277                                                         end
 278                                                         device pnp 2e.6 off  # SFI
 279                                                                 io 0x62 = 0x100
 280                                                         end
 281                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 282                                                                 io 0x60 = 0x220
 283                                                                 io 0x62 = 0x300
 284                                                                 irq 0x70 = 9
 285                                                         end
 286                                                         device pnp 2e.8 off end #  WDTO_PLED
 287                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 288                                                         device pnp 2e.a off end #  ACPI
 289                                                         device pnp 2e.b on #  HW Monitor
 290                                                                 io 0x60 = 0x290
 291                                                                 irq 0x70 = 5
 292                                                         end
 293                                                 end
 294                                         end
 295                                         device pci 1.1 on # SM 0
 296                                                 chip drivers/generic/generic #dimm 0-0-0
 297                                                         device i2c 50 on end
 298                                                 end
 299                                                 chip drivers/generic/generic #dimm 0-0-1
 300                                                         device i2c 51 on end
 301                                                 end
 302                                                 chip drivers/generic/generic #dimm 0-1-0
 303                                                         device i2c 52 on end
 304                                                 end
 305                                                 chip drivers/generic/generic #dimm 0-1-1
 306                                                         device i2c 53 on end
 307                                                 end
 308                                                 chip drivers/generic/generic #dimm 1-0-0
 309                                                         device i2c 54 on end
 310                                                 end
 311                                                 chip drivers/generic/generic #dimm 1-0-1
 312                                                         device i2c 55 on end
 313                                                 end
 314                                                 chip drivers/generic/generic #dimm 1-1-0
 315                                                         device i2c 56 on end
 316                                                 end
 317                                                 chip drivers/generic/generic #dimm 1-1-1
 318                                                         device i2c 57 on end
 319                                                 end
 320                                         end # SM
 321                                         device pci 1.1 on # SM 1
 322 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 323 #                                               chip drivers/generic/generic #PCIXA Slot1
 324 #                                                       device i2c 50 on end
 325 #                                               end
 326 #                                               chip drivers/generic/generic #PCIXB Slot1
 327 #                                                       device i2c 51 on end
 328 #                                               end
 329 #                                               chip drivers/generic/generic #PCIXB Slot2
 330 #                                                       device i2c 52 on end
 331 #                                               end
 332 #                                               chip drivers/generic/generic #PCI Slot1
 333 #                                                       device i2c 53 on end
 334 #                                               end
 335 #                                               chip drivers/generic/generic #Master MCP55 PCI-E
 336 #                                                       device i2c 54 on end
 337 #                                               end
 338 #                                               chip drivers/generic/generic #Slave MCP55 PCI-E
 339 #                                                       device i2c 55 on end
 340 #                                               end
 341                                                 chip drivers/generic/generic #MAC EEPROM
 342                                                         device i2c 51 on end
 343                                                 end
 344
 345                                         end # SM
 346                                         device pci 2.0 on end # USB 1.1
 347                                         device pci 2.1 on end # USB 2
 348                                         device pci 4.0 on end # IDE
 349                                         device pci 5.0 on end # SATA 0
 350                                         device pci 5.1 on end # SATA 1
 351                                         device pci 5.2 on end # SATA 2
 352                                         device pci 6.0 on end # PCI
 353                                         device pci 6.1 on end # AZA
 354                                         device pci 8.0 on end # NIC
 355                                         device pci 9.0 on end # NIC
 356                                         device pci a.0 on end # PCI E 5
 357                                         device pci b.0 off end # PCI E 4
 358                                         device pci c.0 off end # PCI E 3
 359                                         device pci d.0 on end # PCI E 2
 360                                         device pci e.0 off end # PCI E 1
 361                                         device pci f.0 on end # PCI E 0
 362                                         register "ide0_enable" = "1"
 363                                         register "sata0_enable" = "1"
 364                                         register "sata1_enable" = "1"
 365                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 366                                         register "mac_eeprom_addr" = "0x51"
 367                                 end
 368                         end #  device pci 18.0
 369                         device pci 18.0 on end # Link 1
 370                         device pci 18.0 on
 371                                 #  devices on link 2, link 2 == LDT 2
 372                                 chip southbridge/nvidia/mcp55
 373                                         device pci 0.0 on end   # HT
 374                                         device pci 1.0 on end  # LPC
 375                                         device pci 1.1 on end # SM 0
 376                                         device pci 2.0 off end # USB 1.1
 377                                         device pci 2.1 off end # USB 2
 378                                         device pci 4.0 off end # IDE
 379                                         device pci 5.0 on end # SATA 0
 380                                         device pci 5.1 on end # SATA 1
 381                                         device pci 5.2 on end # SATA 2
 382                                         device pci 6.0 off end # PCI
 383                                         device pci 6.1 off end # AZA
 384                                         device pci 8.0 on end # NIC
 385                                         device pci 9.0 on end # NIC
 386                                         device pci a.0 on end # PCI E 5
 387                                         device pci b.0 off end # PCI E 4
 388                                         device pci c.0 off end # PCI E 3
 389                                         device pci d.0 on end # PCI E 2
 390                                         device pci e.0 on end # PCI E 1
 391                                         device pci f.0 on end # PCI E 0
 392                                         register "ide0_enable" = "1"
 393                                         register "sata0_enable" = "1"
 394                                         register "sata1_enable" = "1"
 395                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 396                                         register "mac_eeprom_addr" = "0x51"
 397                                 end
 398                         end # device pci 18.0
 399                         device pci 18.1 on end
 400                         device pci 18.2 on end
 401                         device pci 18.3 on end
 402                 end # mc0
 403
 404         end # PCI domain
 405
 406 #       chip drivers/generic/debug
 407 #               device pnp 0.0 off end # chip name
 408 #               device pnp 0.1 on end # pci_regs_all
 409 #               device pnp 0.2 on end # mem
 410 #               device pnp 0.3 off end # cpuid
 411 #               device pnp 0.4 on end # smbus_regs_all
 412 #               device pnp 0.5 off end # dual core msr
 413 #               device pnp 0.6 off end # cache size
 414 #               device pnp 0.7 off end # tsc
 415 #               device pnp 0.8 off  end # io
 416 #               device pnp 0.9 off end # io
 417 #       end
 418 end #root_complex