2 ## This file is part of the LinuxBIOS project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 ## Compute the location and size of where this firmware image
24 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
27 default ROM_SECTION_SIZE = FAILOVER_SIZE
28 default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
31 default ROM_SECTION_SIZE = FALLBACK_SIZE
32 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
34 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
35 default ROM_SECTION_OFFSET = 0
40 ## Compute the start location and size size of
41 ## The linuxBIOS bootloader.
43 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
47 ## Compute where this copy of linuxBIOS will start in the boot rom
49 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
52 ## Compute a range of ROM that can cached to speed up linuxBIOS,
55 ## XIP_ROM_SIZE must be a power of 2.
56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
58 default XIP_ROM_SIZE=65536
61 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
64 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
66 default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
73 ## Build the objects we have code for in this directory.
77 #needed by irq_tables and mptable and acpi_tables
80 if HAVE_MP_TABLE object mptable.o end
81 if HAVE_PIRQ_TABLE object irq_tables.o end
88 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
89 action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
90 action "mv dsdt_lb.hex dsdt.c"
94 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
98 depends "$(MAINBOARD)/dx/pci6.asl"
99 action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
100 action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
101 action "mv pci6.hex ssdt6.c"
105 depends "$(MAINBOARD)/dx/pci5.asl"
106 action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
107 action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
108 action "mv pci5.hex ssdt5.c"
117 makerule ./cache_as_ram_auto.o
118 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
119 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
122 makerule ./cache_as_ram_auto.inc
123 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
124 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
125 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
126 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
132 if USE_FAILOVER_IMAGE
134 if CONFIG_AP_CODE_IN_CAR
135 makerule ./apc_auto.o
136 depends "$(MAINBOARD)/apc_auto.c option_table.h"
137 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
139 ldscript /arch/i386/init/ldscript_apc.lb
145 ## Build our 16 bit and 32 bit linuxBIOS entry code
147 if HAVE_FAILOVER_BOOT
148 if USE_FAILOVER_IMAGE
149 mainboardinit cpu/x86/16bit/entry16.inc
150 ldscript /cpu/x86/16bit/entry16.lds
153 if USE_FALLBACK_IMAGE
154 mainboardinit cpu/x86/16bit/entry16.inc
155 ldscript /cpu/x86/16bit/entry16.lds
159 mainboardinit cpu/x86/32bit/entry32.inc
163 ldscript /cpu/x86/32bit/entry32.lds
167 ldscript /cpu/amd/car/cache_as_ram.lds
173 ## Build our reset vector (This is where linuxBIOS is entered)
175 if HAVE_FAILOVER_BOOT
176 if USE_FAILOVER_IMAGE
177 mainboardinit cpu/x86/16bit/reset16.inc
178 ldscript /cpu/x86/16bit/reset16.lds
180 mainboardinit cpu/x86/32bit/reset32.inc
181 ldscript /cpu/x86/32bit/reset32.lds
184 if USE_FALLBACK_IMAGE
185 mainboardinit cpu/x86/16bit/reset16.inc
186 ldscript /cpu/x86/16bit/reset16.lds
188 mainboardinit cpu/x86/32bit/reset32.inc
189 ldscript /cpu/x86/32bit/reset32.lds
194 ## Include an id string (For safe flashing)
196 mainboardinit southbridge/nvidia/mcp55/id.inc
197 ldscript /southbridge/nvidia/mcp55/id.lds
200 ## ROMSTRAP table for MCP55
202 if HAVE_FAILOVER_BOOT
203 if USE_FAILOVER_IMAGE
204 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
205 ldscript /southbridge/nvidia/mcp55/romstrap.lds
208 if USE_FALLBACK_IMAGE
209 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
210 ldscript /southbridge/nvidia/mcp55/romstrap.lds
216 ## Setup Cache-As-Ram
218 mainboardinit cpu/amd/car/cache_as_ram.inc
222 ### This is the early phase of linuxBIOS startup
223 ### Things are delicate and we test to see if we should
224 ### failover to another image.
226 if HAVE_FAILOVER_BOOT
227 if USE_FAILOVER_IMAGE
229 ldscript /arch/i386/lib/failover_failover.lds
233 if USE_FALLBACK_IMAGE
235 ldscript /arch/i386/lib/failover.lds
246 initobject cache_as_ram_auto.o
248 mainboardinit ./cache_as_ram_auto.inc
253 ## Include the secondary Configuration files
259 chip northbridge/amd/amdk8/root_complex
260 device apic_cluster 0 on
261 chip cpu/amd/socket_F
265 device pci_domain 0 on
266 chip northbridge/amd/amdk8 #mc0
268 # devices on link 0, link 0 == LDT 0
269 chip southbridge/nvidia/mcp55
270 device pci 0.0 on end # HT
271 device pci 1.0 on # LPC
272 chip superio/winbond/w83627ehg
273 device pnp 2e.0 off # Floppy
278 device pnp 2e.1 off # Parallel Port
282 device pnp 2e.2 on # Com1
286 device pnp 2e.3 off # Com2
290 device pnp 2e.5 on # Keyboard
296 device pnp 2e.6 off # SFI
299 device pnp 2e.7 off # GPIO_GAME_MIDI
304 device pnp 2e.8 off end # WDTO_PLED
305 device pnp 2e.9 off end # GPIO_SUSLED
306 device pnp 2e.a off end # ACPI
307 device pnp 2e.b on # HW Monitor
313 device pci 1.1 on # SM 0
314 chip drivers/generic/generic #dimm 0-0-0
317 chip drivers/generic/generic #dimm 0-0-1
320 chip drivers/generic/generic #dimm 0-1-0
323 chip drivers/generic/generic #dimm 0-1-1
326 chip drivers/generic/generic #dimm 1-0-0
329 chip drivers/generic/generic #dimm 1-0-1
332 chip drivers/generic/generic #dimm 1-1-0
335 chip drivers/generic/generic #dimm 1-1-1
339 device pci 1.1 on # SM 1
340 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
341 # chip drivers/generic/generic #PCIXA Slot1
342 # device i2c 50 on end
344 # chip drivers/generic/generic #PCIXB Slot1
345 # device i2c 51 on end
347 # chip drivers/generic/generic #PCIXB Slot2
348 # device i2c 52 on end
350 # chip drivers/generic/generic #PCI Slot1
351 # device i2c 53 on end
353 # chip drivers/generic/generic #Master MCP55 PCI-E
354 # device i2c 54 on end
356 # chip drivers/generic/generic #Slave MCP55 PCI-E
357 # device i2c 55 on end
359 chip drivers/generic/generic #MAC EEPROM
364 device pci 2.0 on end # USB 1.1
365 device pci 2.1 on end # USB 2
366 device pci 4.0 on end # IDE
367 device pci 5.0 on end # SATA 0
368 device pci 5.1 on end # SATA 1
369 device pci 5.2 on end # SATA 2
370 device pci 6.0 on end # PCI
371 device pci 6.1 on end # AZA
372 device pci 8.0 on end # NIC
373 device pci 9.0 on end # NIC
374 device pci a.0 on end # PCI E 5
375 device pci b.0 off end # PCI E 4
376 device pci c.0 off end # PCI E 3
377 device pci d.0 on end # PCI E 2
378 device pci e.0 off end # PCI E 1
379 device pci f.0 on end # PCI E 0
380 register "ide0_enable" = "1"
381 register "sata0_enable" = "1"
382 register "sata1_enable" = "1"
383 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
384 register "mac_eeprom_addr" = "0x51"
386 end # device pci 18.0
387 device pci 18.0 on end # Link 1
389 # devices on link 2, link 2 == LDT 2
390 chip southbridge/nvidia/mcp55
391 device pci 0.0 on end # HT
392 device pci 1.0 on end # LPC
393 device pci 1.1 on end # SM 0
394 device pci 2.0 off end # USB 1.1
395 device pci 2.1 off end # USB 2
396 device pci 4.0 off end # IDE
397 device pci 5.0 on end # SATA 0
398 device pci 5.1 on end # SATA 1
399 device pci 5.2 on end # SATA 2
400 device pci 6.0 off end # PCI
401 device pci 6.1 off end # AZA
402 device pci 8.0 on end # NIC
403 device pci 9.0 on end # NIC
404 device pci a.0 on end # PCI E 5
405 device pci b.0 off end # PCI E 4
406 device pci c.0 off end # PCI E 3
407 device pci d.0 on end # PCI E 2
408 device pci e.0 on end # PCI E 1
409 device pci f.0 on end # PCI E 0
410 register "ide0_enable" = "1"
411 register "sata0_enable" = "1"
412 register "sata1_enable" = "1"
413 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
414 register "mac_eeprom_addr" = "0x51"
416 end # device pci 18.0
417 device pci 18.1 on end
418 device pci 18.2 on end
419 device pci 18.3 on end
424 # chip drivers/generic/debug
425 # device pnp 0.0 off end # chip name
426 # device pnp 0.1 on end # pci_regs_all
427 # device pnp 0.2 on end # mem
428 # device pnp 0.3 off end # cpuid
429 # device pnp 0.4 on end # smbus_regs_all
430 # device pnp 0.5 off end # dual core msr
431 # device pnp 0.6 off end # cache size
432 # device pnp 0.7 off end # tsc
433 # device pnp 0.8 off end # io
434 # device pnp 0.9 off end # io