src/mainboard/newisys/khepri/romstage.c

   1 /*
   2  * This code is derived from the Tyan s2882 romstage.c
   3  * Adapted by Stefan Reinauer <stepan@coresystems.de>
   4  * Additional (C) 2007 coresystems GmbH
   5  */
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <pc80/mc146818rtc.h>
  14 #include <console/console.h>
  15 #include <lib.h>
  16 #include <spd.h>
  17 #include <cpu/amd/model_fxx_rev.h>
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/amd/amd8111/early_smbus.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "superio/winbond/w83627hf/early_serial.c"
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29 #include "southbridge/amd/amd8111/early_ctrl.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 static void memreset_setup(void)
  34 {
  35         if (is_cpu_pre_c0()) {
  36                 /* Set the memreset low. */
  37                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  38                 /* Ensure the BIOS has control of the memory lines. */
  39                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  40         } else {
  41                 /* Ensure the CPU has control of the memory lines. */
  42                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  43         }
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48         if (is_cpu_pre_c0()) {
  49                 udelay(800);
  50                 /* Set memreset high. */
  51                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  52                 udelay(90);
  53         }
  54 }
  55
  56 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  57
  58 static inline int spd_read_byte(unsigned device, unsigned address)
  59 {
  60         return smbus_read_byte(device, address);
  61 }
  62
  63 #include "northbridge/amd/amdk8/raminit.c"
  64 #include "northbridge/amd/amdk8/coherent_ht.c"
  65 #include "lib/generic_sdram.c"
  66 #include "resourcemap.c"
  67 #include "cpu/amd/dualcore/dualcore.c"
  68 #include "cpu/amd/car/post_cache_as_ram.c"
  69 #include "cpu/amd/model_fxx/init_cpus.c"
  70
  71 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  72 {
  73         static const uint16_t spd_addr [] = {
  74                 DIMM0, DIMM2, 0, 0,
  75                 DIMM1, DIMM3, 0, 0,
  76 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  77                 DIMM4, DIMM6, 0, 0,
  78                 DIMM5, DIMM7, 0, 0,
  79 #endif
  80         };
  81
  82         int needs_reset;
  83         unsigned bsp_apicid = 0, nodes;
  84         struct mem_controller ctrl[8];
  85
  86         if (bist == 0)
  87                 bsp_apicid = init_cpus(cpu_init_detectedx);
  88
  89         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  90         console_init();
  91
  92 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
  93
  94         /* Halt if there was a built in self test failure */
  95         report_bist_failure(bist);
  96
  97         setup_khepri_resource_map();
  98 #if 0
  99         dump_pci_device(PCI_DEV(0, 0x18, 0));
 100         dump_pci_device(PCI_DEV(0, 0x19, 0));
 101 #endif
 102
 103         needs_reset = setup_coherent_ht_domain();
 104
 105         wait_all_core0_started();
 106 #if CONFIG_LOGICAL_CPUS==1
 107         // It is said that we should start core1 after all core0 launched
 108         start_other_cores();
 109         wait_all_other_cores_started(bsp_apicid);
 110 #endif
 111
 112         needs_reset |= ht_setup_chains_x();
 113
 114         if (needs_reset) {
 115                 print_info("ht reset -\n");
 116                 soft_reset();
 117         }
 118
 119         allow_all_aps_stop(bsp_apicid);
 120
 121         nodes = get_nodes();
 122         //It's the time to set ctrl now;
 123         fill_mem_ctrl(nodes, ctrl, spd_addr);
 124
 125         enable_smbus();
 126
 127         memreset_setup();
 128         sdram_initialize(nodes, ctrl);
 129
 130 #if 0
 131         dump_pci_devices();
 132 #endif
 133
 134         post_cache_as_ram();
 135 }