2 * This code is derived from the Tyan s2882 romstage.c
3 * Adapted by Stefan Reinauer <stepan@coresystems.de>
4 * Additional (C) 2007 coresystems GmbH
9 #include <device/pci_def.h>
11 #include <device/pnp_def.h>
12 #include <arch/romcc_io.h>
13 #include <cpu/x86/lapic.h>
14 #include <pc80/mc146818rtc.h>
15 #include <console/console.h>
18 #include <cpu/amd/model_fxx_rev.h>
19 #include "northbridge/amd/amdk8/incoherent_ht.c"
20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
21 #include "northbridge/amd/amdk8/raminit.h"
22 #include "cpu/amd/model_fxx/apic_timer.c"
23 #include "lib/delay.c"
24 #include "cpu/x86/lapic/boot_cpu.c"
25 #include "northbridge/amd/amdk8/reset_test.c"
26 #include "northbridge/amd/amdk8/debug.c"
27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
28 #include "cpu/x86/mtrr/earlymtrr.c"
29 #include "cpu/x86/bist.h"
30 #include "northbridge/amd/amdk8/setup_resource_map.c"
31 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
35 static void memreset_setup(void)
37 if (is_cpu_pre_c0()) {
38 /* Set the memreset low. */
39 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
40 /* Ensure the BIOS has control of the memory lines. */
41 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
43 /* Ensure the CPU has control of the memory lines. */
44 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
48 static void memreset(int controllers, const struct mem_controller *ctrl)
50 if (is_cpu_pre_c0()) {
52 /* Set memreset high. */
53 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
58 static void activate_spd_rom(const struct mem_controller *ctrl) { }
60 static inline int spd_read_byte(unsigned device, unsigned address)
62 return smbus_read_byte(device, address);
65 #include "northbridge/amd/amdk8/raminit.c"
66 #include "northbridge/amd/amdk8/coherent_ht.c"
67 #include "lib/generic_sdram.c"
68 #include "resourcemap.c"
69 #include "cpu/amd/dualcore/dualcore.c"
70 #include "cpu/amd/car/post_cache_as_ram.c"
71 #include "cpu/amd/model_fxx/init_cpus.c"
72 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
73 #include "northbridge/amd/amdk8/early_ht.c"
75 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
77 static const uint16_t spd_addr [] = {
80 #if CONFIG_MAX_PHYSICAL_CPUS > 1
87 unsigned bsp_apicid = 0, nodes;
88 struct mem_controller ctrl[8];
90 if (!cpu_init_detectedx && boot_cpu()) {
91 /* Nothing special needs to be done to find bus 0 */
92 /* Allow the HT devices to be found */
98 bsp_apicid = init_cpus(cpu_init_detectedx);
100 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
104 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
106 /* Halt if there was a built in self test failure */
107 report_bist_failure(bist);
109 setup_khepri_resource_map();
111 dump_pci_device(PCI_DEV(0, 0x18, 0));
112 dump_pci_device(PCI_DEV(0, 0x19, 0));
115 needs_reset = setup_coherent_ht_domain();
117 wait_all_core0_started();
118 #if CONFIG_LOGICAL_CPUS==1
119 // It is said that we should start core1 after all core0 launched
121 wait_all_other_cores_started(bsp_apicid);
124 needs_reset |= ht_setup_chains_x();
127 print_info("ht reset -\n");
131 allow_all_aps_stop(bsp_apicid);
134 //It's the time to set ctrl now;
135 fill_mem_ctrl(nodes, ctrl, spd_addr);
140 sdram_initialize(nodes, ctrl);