src/mainboard/newisys/khepri/romstage.c

   1 /*
   2  * This code is derived from the Tyan s2882 romstage.c
   3  * Adapted by Stefan Reinauer <stepan@coresystems.de>
   4  * Additional (C) 2007 coresystems GmbH
   5  */
   6 #define ASSEMBLY 1
   7 #define __PRE_RAM__
   8
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <device/pci_def.h>
  12 #include <arch/io.h>
  13 #include <device/pnp_def.h>
  14 #include <arch/romcc_io.h>
  15 #include <cpu/x86/lapic.h>
  16 #include "option_table.h"
  17 #include "pc80/mc146818rtc_early.c"
  18 #include "pc80/serial.c"
  19 #include "arch/i386/lib/console.c"
  20 #include "lib/ramtest.c"
  21
  22 #if 0
  23 static void post_code(uint8_t value) {
  24 #if 1
  25         int i;
  26         for(i=0;i<0x80000;i++) {
  27                 outb(value, 0x80);
  28         }
  29 #endif
  30 }
  31 #endif
  32
  33 #include <cpu/amd/model_fxx_rev.h>
  34
  35 #include "northbridge/amd/amdk8/incoherent_ht.c"
  36 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  37 #include "northbridge/amd/amdk8/raminit.h"
  38 #include "cpu/amd/model_fxx/apic_timer.c"
  39 #include "lib/delay.c"
  40
  41 #include "cpu/x86/lapic/boot_cpu.c"
  42 #include "northbridge/amd/amdk8/reset_test.c"
  43 #include "northbridge/amd/amdk8/debug.c"
  44 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  45
  46 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48
  49 #include "northbridge/amd/amdk8/setup_resource_map.c"
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  52
  53 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  54
  55 static void memreset_setup(void)
  56 {
  57         if (is_cpu_pre_c0()) {
  58                 /* Set the memreset low */
  59                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  60                 /* Ensure the BIOS has control of the memory lines */
  61                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  62         }
  63         else {
  64                 /* Ensure the CPU has controll of the memory lines */
  65                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  66         }
  67 }
  68
  69 static void memreset(int controllers, const struct mem_controller *ctrl)
  70 {
  71         if (is_cpu_pre_c0()) {
  72                 udelay(800);
  73                 /* Set memreset_high */
  74                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  75                 udelay(90);
  76         }
  77 }
  78
  79 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  80 {
  81         /* nothing to do */
  82 }
  83
  84 static inline int spd_read_byte(unsigned device, unsigned address)
  85 {
  86         return smbus_read_byte(device, address);
  87 }
  88
  89 #define QRANK_DIMM_SUPPORT 1
  90
  91 #include "northbridge/amd/amdk8/raminit.c"
  92 #include "northbridge/amd/amdk8/coherent_ht.c"
  93 #include "lib/generic_sdram.c"
  94
  95  /* newisys khepri does not want the default */
  96 #include "resourcemap.c"
  97
  98 #if CONFIG_LOGICAL_CPUS==1
  99 #define SET_NB_CFG_54 1
 100 #endif
 101 #include "cpu/amd/dualcore/dualcore.c"
 102
 103
 104 #include "cpu/amd/car/copy_and_run.c"
 105
 106 #include "cpu/amd/car/post_cache_as_ram.c"
 107
 108 #include "cpu/amd/model_fxx/init_cpus.c"
 109
 110
 111 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 112 #include "northbridge/amd/amdk8/early_ht.c"
 113
 114 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 115 {
 116         static const uint16_t spd_addr [] = {
 117                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 118                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 119 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 120                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 121                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 122 #endif
 123         };
 124
 125         int needs_reset;
 126         unsigned bsp_apicid = 0;
 127
 128         struct mem_controller ctrl[8];
 129         unsigned nodes;
 130
 131         if (!cpu_init_detectedx && boot_cpu()) {
 132                 /* Nothing special needs to be done to find bus 0 */
 133                 /* Allow the HT devices to be found */
 134
 135                 enumerate_ht_chain();
 136
 137                 /* Setup the amd8111 */
 138                 amd8111_enable_rom();
 139         }
 140
 141         if (bist == 0) {
 142                 bsp_apicid = init_cpus(cpu_init_detectedx);
 143         }
 144
 145 //      post_code(0x32);
 146
 147         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 148         uart_init();
 149         console_init();
 150
 151 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 152
 153         /* Halt if there was a built in self test failure */
 154         report_bist_failure(bist);
 155
 156         setup_khepri_resource_map();
 157 #if 0
 158         dump_pci_device(PCI_DEV(0, 0x18, 0));
 159         dump_pci_device(PCI_DEV(0, 0x19, 0));
 160 #endif
 161
 162         needs_reset = setup_coherent_ht_domain();
 163
 164         wait_all_core0_started();
 165 #if CONFIG_LOGICAL_CPUS==1
 166         // It is said that we should start core1 after all core0 launched
 167         start_other_cores();
 168         wait_all_other_cores_started(bsp_apicid);
 169 #endif
 170
 171         needs_reset |= ht_setup_chains_x();
 172
 173         if (needs_reset) {
 174                 print_info("ht reset -\r\n");
 175                 soft_reset();
 176         }
 177
 178
 179         allow_all_aps_stop(bsp_apicid);
 180
 181         nodes = get_nodes();
 182         //It's the time to set ctrl now;
 183         fill_mem_ctrl(nodes, ctrl, spd_addr);
 184
 185         enable_smbus();
 186
 187         memreset_setup();
 188         sdram_initialize(nodes, ctrl);
 189
 190 #if 0
 191         dump_pci_devices();
 192 #endif
 193
 194         post_cache_as_ram();
 195
 196 }