src/mainboard/newisys/khepri/cache_as_ram_auto.c

   1 /*
   2  * This code is derived from the Tyan s2882 cache_as_ram_auto.c
   3  * Adapted by Stefan Reinauer <stepan@coresystems.de>
   4  * Additional (C) 2007 coresystems GmbH
   5  */
   6 #define ASSEMBLY 1
   7 #define __ROMCC__
   8
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <device/pci_def.h>
  12 #include <arch/io.h>
  13 #include <device/pnp_def.h>
  14 #include <arch/romcc_io.h>
  15 #include <cpu/x86/lapic.h>
  16 #include "option_table.h"
  17 #include "pc80/mc146818rtc_early.c"
  18 #include "pc80/serial.c"
  19 #include "arch/i386/lib/console.c"
  20 #include "ram/ramtest.c"
  21
  22 #if 0
  23 static void post_code(uint8_t value) {
  24 #if 1
  25         int i;
  26         for(i=0;i<0x80000;i++) {
  27                 outb(value, 0x80);
  28         }
  29 #endif
  30 }
  31 #endif
  32
  33 #include <cpu/amd/model_fxx_rev.h>
  34
  35 #include "northbridge/amd/amdk8/incoherent_ht.c"
  36 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  37 #include "northbridge/amd/amdk8/raminit.h"
  38 #include "cpu/amd/model_fxx/apic_timer.c"
  39 #include "lib/delay.c"
  40
  41 #include "cpu/x86/lapic/boot_cpu.c"
  42 #include "northbridge/amd/amdk8/reset_test.c"
  43 #include "northbridge/amd/amdk8/debug.c"
  44 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  45
  46 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48
  49 #include "northbridge/amd/amdk8/setup_resource_map.c"
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  52
  53 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  54
  55 static void memreset_setup(void)
  56 {
  57         if (is_cpu_pre_c0()) {
  58                 /* Set the memreset low */
  59                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  60                 /* Ensure the BIOS has control of the memory lines */
  61                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  62         }
  63         else {
  64                 /* Ensure the CPU has controll of the memory lines */
  65                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  66         }
  67 }
  68
  69 static void memreset(int controllers, const struct mem_controller *ctrl)
  70 {
  71         if (is_cpu_pre_c0()) {
  72                 udelay(800);
  73                 /* Set memreset_high */
  74                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  75                 udelay(90);
  76         }
  77 }
  78
  79 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  80 {
  81         /* nothing to do */
  82 }
  83
  84 static inline int spd_read_byte(unsigned device, unsigned address)
  85 {
  86         return smbus_read_byte(device, address);
  87 }
  88
  89 #define QRANK_DIMM_SUPPORT 1
  90
  91 #include "northbridge/amd/amdk8/raminit.c"
  92 #include "northbridge/amd/amdk8/coherent_ht.c"
  93 #include "sdram/generic_sdram.c"
  94
  95  /* newisys khepri does not want the default */
  96 #include "resourcemap.c"
  97
  98 #if CONFIG_LOGICAL_CPUS==1
  99 #define SET_NB_CFG_54 1
 100 #endif
 101 #include "cpu/amd/dualcore/dualcore.c"
 102
 103
 104 #include "cpu/amd/car/copy_and_run.c"
 105
 106 #include "cpu/amd/car/post_cache_as_ram.c"
 107
 108 #include "cpu/amd/model_fxx/init_cpus.c"
 109
 110
 111 #if USE_FALLBACK_IMAGE == 1
 112
 113 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 114 #include "northbridge/amd/amdk8/early_ht.c"
 115
 116 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 117 {
 118         unsigned last_boot_normal_x = last_boot_normal();
 119
 120         /* Is this a cpu only reset? or Is this a secondary cpu? */
 121         if ((cpu_init_detectedx) || (!boot_cpu())) {
 122                 if (last_boot_normal_x) {
 123                         goto normal_image;
 124                 } else {
 125                         goto fallback_image;
 126                 }
 127         }
 128
 129         /* Nothing special needs to be done to find bus 0 */
 130         /* Allow the HT devices to be found */
 131
 132         enumerate_ht_chain();
 133
 134         /* Setup the ck804 */
 135         amd8111_enable_rom();
 136
 137         /* Is this a deliberate reset by the bios */
 138 //        post_code(0x22);
 139         if (bios_reset_detected() && last_boot_normal_x) {
 140                 goto normal_image;
 141         }
 142         /* This is the primary cpu how should I boot? */
 143         else if (do_normal_boot()) {
 144                 goto normal_image;
 145         }
 146         else {
 147                 goto fallback_image;
 148         }
 149  normal_image:
 150 //        post_code(0x23);
 151         __asm__ volatile ("jmp __normal_image"
 152                 : /* outputs */
 153                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 154                 );
 155
 156  fallback_image:
 157 //        post_code(0x25);
 158         ;
 159 }
 160 #endif
 161
 162 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 163
 164 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 165 {
 166
 167 #if USE_FALLBACK_IMAGE == 1
 168         failover_process(bist, cpu_init_detectedx);
 169 #endif
 170         real_main(bist, cpu_init_detectedx);
 171
 172 }
 173
 174 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 175 {
 176         static const uint16_t spd_addr [] = {
 177                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 178                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 179 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 180                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 181                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 182 #endif
 183         };
 184
 185         int needs_reset;
 186         unsigned bsp_apicid = 0;
 187
 188         struct mem_controller ctrl[8];
 189         unsigned nodes;
 190
 191         if (bist == 0) {
 192                 bsp_apicid = init_cpus(cpu_init_detectedx);
 193         }
 194
 195 //      post_code(0x32);
 196
 197         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 198         uart_init();
 199         console_init();
 200
 201 //      dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
 202
 203         /* Halt if there was a built in self test failure */
 204         report_bist_failure(bist);
 205
 206         setup_khepri_resource_map();
 207 #if 0
 208         dump_pci_device(PCI_DEV(0, 0x18, 0));
 209         dump_pci_device(PCI_DEV(0, 0x19, 0));
 210 #endif
 211
 212         needs_reset = setup_coherent_ht_domain();
 213
 214         wait_all_core0_started();
 215 #if CONFIG_LOGICAL_CPUS==1
 216         // It is said that we should start core1 after all core0 launched
 217         start_other_cores();
 218         wait_all_other_cores_started(bsp_apicid);
 219 #endif
 220
 221         needs_reset |= ht_setup_chains_x();
 222
 223         if (needs_reset) {
 224                 print_info("ht reset -\r\n");
 225                 soft_reset();
 226         }
 227
 228
 229         allow_all_aps_stop(bsp_apicid);
 230
 231         nodes = get_nodes();
 232         //It's the time to set ctrl now;
 233         fill_mem_ctrl(nodes, ctrl, spd_addr);
 234
 235         enable_smbus();
 236
 237         memreset_setup();
 238         sdram_initialize(nodes, ctrl);
 239
 240 #if 0
 241         dump_pci_devices();
 242 #endif
 243
 244         post_cache_as_ram();
 245
 246 }