src/mainboard/newisys/khepri/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <arch/cpu.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "northbridge/amd/amdk8/incoherent_ht.c"
  22 #include "northbridge/amd/amdk8/cpu_rev.c"
  23 #include "superio/NSC/pc87360/pc87360_early_serial.c"
  24 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  28
  29 static void hard_reset(void)
  30 {
  31         set_bios_reset();
  32
  33         /* enable cf9 */
  34         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  35         /* reset */
  36         outb(0x0e, 0x0cf9);
  37 }
  38
  39 static void soft_reset(void)
  40 {
  41         set_bios_reset();
  42         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  43 }
  44
  45 static void memreset_setup(void)
  46 {
  47         if (is_cpu_pre_c0()) {
  48                 /* Set the memreset low */
  49                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  50                 /* Ensure the BIOS has control of the memory lines */
  51                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  52         }
  53         else {
  54                 /* Ensure the CPU has controll of the memory lines */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  56         }
  57 }
  58
  59 static void memreset(int controllers, const struct mem_controller *ctrl)
  60 {
  61         if (is_cpu_pre_c0()) {
  62                 udelay(800);
  63                 /* Set memreset_high */
  64                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  65                 udelay(90);
  66         }
  67 }
  68
  69 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  70 {
  71         /* nothing to do */
  72 }
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/amd/amdk8/raminit.c"
  80
  81 #include "northbridge/amd/amdk8/coherent_ht.c"
  82
  83 #include "sdram/generic_sdram.c"
  84
  85 /* newisys khepri does not want the default */
  86 #include "resourcemap.c"
  87
  88 #define NODE_RAM(x)                     \
  89         .node_id = 0+x,                 \
  90         .f0 = PCI_DEV(0, 0x18+x, 0),    \
  91         .f1 = PCI_DEV(0, 0x18+x, 1),    \
  92         .f2 = PCI_DEV(0, 0x18+x, 2),    \
  93         .f3 = PCI_DEV(0, 0x18+x, 3)
  94
  95 static void main(unsigned long bist)
  96 {
  97         static const struct mem_controller cpu[] = {
  98                 {
  99                         NODE_RAM(0),
 100                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 101                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 102                 },
 103                 {
 104                         NODE_RAM(1),
 105                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 106                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 107                 },
 108         };
 109
 110         int needs_reset;
 111         unsigned nodeid;
 112
 113         if (bist == 0) {
 114                 /* Skip this if there was a built in self test failure */
 115                 amd_early_mtrr_init();
 116                 enable_lapic();
 117                 init_timer();
 118
 119                 nodeid = lapicid() & 0xf;
 120
 121                 /* Has this cpu already booted? */
 122                 if (cpu_init_detected(nodeid)) {
 123                         asm volatile ("jmp __cpu_reset");
 124                 }
 125                 distinguish_cpu_resets(nodeid);
 126                 if (!boot_cpu()) {
 127                         stop_this_cpu();
 128                 }
 129         }
 130         /* Setup the console */
 131         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 132         uart_init();
 133         console_init();
 134
 135         /* Halt if there was a built in self test failure */
 136         report_bist_failure(bist);
 137
 138         setup_khepri_resource_map();
 139         needs_reset = setup_coherent_ht_domain();
 140         needs_reset=ht_setup_chains_x();
 141
 142         if (needs_reset) {
 143                 print_info("ht reset -\r\n");
 144                 soft_reset();
 145         }
 146 #if 0
 147         print_pci_devices();
 148 #endif
 149         enable_smbus();
 150 #if 0
 151         dump_spd_registers(&cpu[0]);
 152 #endif
 153         memreset_setup();
 154         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 155
 156 #if 0
 157         dump_pci_devices();
 158 #endif
 159 #if 0
 160         dump_pci_device(PCI_DEV(0, 0x18, 2));
 161 #endif
 162
 163 #if 0
 164         /* Check the first 1M */
 165         ram_check(0x00000000, 0x000100000);
 166 #endif
 167 }