src/mainboard/newisys/khepri/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <arch/cpu.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include <cpu/amd/model_fxx_rev.h>
  22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  23 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  24 #include "cpu/x86/bist.h"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  27
  28 static void hard_reset(void)
  29 {
  30         set_bios_reset();
  31
  32         /* enable cf9 */
  33         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  34         /* reset */
  35         outb(0x0e, 0x0cf9);
  36 }
  37
  38 static void soft_reset(void)
  39 {
  40         set_bios_reset();
  41         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  42 }
  43
  44 static void memreset_setup(void)
  45 {
  46         if (is_cpu_pre_c0()) {
  47                 /* Set the memreset low */
  48                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  49                 /* Ensure the BIOS has control of the memory lines */
  50                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  51         }
  52         else {
  53                 /* Ensure the CPU has controll of the memory lines */
  54                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  55         }
  56 }
  57
  58 static void memreset(int controllers, const struct mem_controller *ctrl)
  59 {
  60         if (is_cpu_pre_c0()) {
  61                 udelay(800);
  62                 /* Set memreset_high */
  63                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  64                 udelay(90);
  65         }
  66 }
  67
  68 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  69 {
  70         /* nothing to do */
  71 }
  72
  73 static inline int spd_read_byte(unsigned device, unsigned address)
  74 {
  75         return smbus_read_byte(device, address);
  76 }
  77
  78 #include "northbridge/amd/amdk8/raminit.c"
  79
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "northbridge/amd/amdk8/incoherent_ht.c"
  82
  83 #include "sdram/generic_sdram.c"
  84
  85 /* newisys khepri does not want the default */
  86 #include "resourcemap.c"
  87 #include "cpu/amd/dualcore/dualcore.c"
  88
  89 #define NODE_RAM(x)                     \
  90         .node_id = 0+x,                 \
  91         .f0 = PCI_DEV(0, 0x18+x, 0),    \
  92         .f1 = PCI_DEV(0, 0x18+x, 1),    \
  93         .f2 = PCI_DEV(0, 0x18+x, 2),    \
  94         .f3 = PCI_DEV(0, 0x18+x, 3)
  95
  96 static void main(unsigned long bist)
  97 {
  98         static const struct mem_controller cpu[] = {
  99                 {
 100                         NODE_RAM(0),
 101                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 102                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 103                 },
 104                 {
 105                         NODE_RAM(1),
 106                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 107                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 108                 },
 109         };
 110
 111         int needs_reset;
 112         unsigned nodeid;
 113
 114         if (bist == 0) {
 115                 k8_init_and_stop_secondaries();
 116         }
 117         /* Setup the console */
 118         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 119         uart_init();
 120         console_init();
 121
 122         /* Halt if there was a built in self test failure */
 123         report_bist_failure(bist);
 124
 125         setup_khepri_resource_map();
 126         needs_reset = setup_coherent_ht_domain();
 127         needs_reset=ht_setup_chains_x();
 128
 129         if (needs_reset) {
 130                 print_info("ht reset -\r\n");
 131                 soft_reset();
 132         }
 133 #if 0
 134         print_pci_devices();
 135 #endif
 136         enable_smbus();
 137 #if 0
 138         dump_spd_registers(&cpu[0]);
 139 #endif
 140         memreset_setup();
 141         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 142
 143 #if 0
 144         dump_pci_devices();
 145 #endif
 146 #if 0
 147         dump_pci_device(PCI_DEV(0, 0x18, 2));
 148 #endif
 149
 150 #if 0
 151         /* Check the first 1M */
 152         ram_check(0x00000000, 0x000100000);
 153 #endif
 154 }