2 #define MAXIMUM_CONSOLE_LOGLEVEL 9
3 #define DEFAULT_CONSOLE_LOGLEVEL 9
6 #include <device/pci_def.h>
8 #include <device/pnp_def.h>
9 #include <arch/romcc_io.h>
10 #include <arch/smp/lapic.h>
11 #include "option_table.h"
12 #include "pc80/mc146818rtc_early.c"
13 #include "pc80/serial.c"
14 #include "arch/i386/lib/console.c"
15 #include "ram/ramtest.c"
16 #include "northbridge/amd/amdk8/incoherent_ht.c"
17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
18 #include "northbridge/amd/amdk8/raminit.h"
19 #include "cpu/k8/apic_timer.c"
20 #include "lib/delay.c"
21 #include "cpu/p6/boot_cpu.c"
22 #include "northbridge/amd/amdk8/reset_test.c"
23 #include "northbridge/amd/amdk8/debug.c"
24 #include "northbridge/amd/amdk8/cpu_rev.c"
25 #include "superio/NSC/pc87360/pc87360_early_serial.c"
27 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
29 static void hard_reset(void)
34 pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
39 static void soft_reset(void)
42 pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
45 static void memreset_setup(void)
47 if (is_cpu_pre_c0()) {
48 /* Set the memreset low */
49 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
50 /* Ensure the BIOS has control of the memory lines */
51 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
54 /* Ensure the CPU has controll of the memory lines */
55 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
59 static void memreset(int controllers, const struct mem_controller *ctrl)
61 if (is_cpu_pre_c0()) {
63 /* Set memreset_high */
64 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
69 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
71 /* Routing Table Node i
73 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
74 * i: 0, 1, 2, 3, 4, 5, 6, 7
76 * [ 0: 3] Request Route
77 * [0] Route to this node
81 * [11: 8] Response Route
82 * [0] Route to this node
86 * [19:16] Broadcast route
87 * [0] Route to this node
93 uint32_t ret=0x00010101; /* default row entry */
95 static const unsigned int rows_2p[2][2] = {
96 { 0x00090101, 0x00010808 },
97 { 0x00010404, 0x00050101 }
101 print_debug("this mainboard is only designed for 2 cpus\r\n");
106 if (!(node >= maxnodes || row >= maxnodes)) {
107 ret=rows_2p[node][row];
113 static inline void activate_spd_rom(const struct mem_controller *ctrl)
118 static inline int spd_read_byte(unsigned device, unsigned address)
120 return smbus_read_byte(device, address);
123 #include "northbridge/amd/amdk8/raminit.c"
125 #include "northbridge/amd/amdk8/coherent_ht.c"
127 #include "sdram/generic_sdram.c"
129 #include "resourcemap.c" /* newisys khepri does not want the default */
131 static void main(void)
134 * GPIO28 of 8111 will control H0_MEMRESET_L
135 * GPIO29 of 8111 will control H1_MEMRESET_L
137 static const struct mem_controller cpu[] = {
140 .f0 = PCI_DEV(0, 0x18, 0),
141 .f1 = PCI_DEV(0, 0x18, 1),
142 .f2 = PCI_DEV(0, 0x18, 2),
143 .f3 = PCI_DEV(0, 0x18, 3),
144 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
145 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
149 .f0 = PCI_DEV(0, 0x19, 0),
150 .f1 = PCI_DEV(0, 0x19, 1),
151 .f2 = PCI_DEV(0, 0x19, 2),
152 .f3 = PCI_DEV(0, 0x19, 3),
153 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
154 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
160 if (cpu_init_detected()) {
161 asm("jmp __cpu_reset");
163 distinguish_cpu_resets();
167 pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
170 setup_khepri_resource_map();
171 needs_reset = setup_coherent_ht_domain();
172 needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
174 print_info("ht reset -\r\n");
182 dump_spd_registers(&cpu[0]);
185 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
191 dump_pci_device(PCI_DEV(0, 0x18, 2));
195 /* Check the first 1M */
196 ram_check(0x00000000, 0x000100000);