src/mainboard/newisys/khepri/auto.c

   1 #define ASSEMBLY 1
   2 #undef MAXIMUM_CONSOLE_LOGLEVEL
   3 #undef DEFAULT_CONSOLE_LOGLEVEL
   4 #define MAXIMUM_CONSOLE_LOGLEVEL 9
   5 #define DEFAULT_CONSOLE_LOGLEVEL 9
   6
   7 #include <stdint.h>
   8 #include <device/pci_def.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <arch/cpu.h>
  14 #include "option_table.h"
  15 #include "pc80/mc146818rtc_early.c"
  16 #include "pc80/serial.c"
  17 #include "arch/i386/lib/console.c"
  18 #include "ram/ramtest.c"
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24 #include "cpu/x86/lapic/boot_cpu.c"
  25 #include "northbridge/amd/amdk8/reset_test.c"
  26 #include "northbridge/amd/amdk8/debug.c"
  27 #include "northbridge/amd/amdk8/cpu_rev.c"
  28 #include "superio/NSC/pc87360/pc87360_early_serial.c"
  29 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  30 #include "cpu/x86/bist.h"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  33
  34 static void hard_reset(void)
  35 {
  36         set_bios_reset();
  37
  38         /* enable cf9 */
  39         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  40         /* reset */
  41         outb(0x0e, 0x0cf9);
  42 }
  43
  44 static void soft_reset(void)
  45 {
  46         set_bios_reset();
  47         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  48 }
  49
  50 static void memreset_setup(void)
  51 {
  52         if (is_cpu_pre_c0()) {
  53                 /* Set the memreset low */
  54                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  55                 /* Ensure the BIOS has control of the memory lines */
  56                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  57         }
  58         else {
  59                 /* Ensure the CPU has controll of the memory lines */
  60                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  61         }
  62 }
  63
  64 static void memreset(int controllers, const struct mem_controller *ctrl)
  65 {
  66         if (is_cpu_pre_c0()) {
  67                 udelay(800);
  68                 /* Set memreset_high */
  69                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  70                 udelay(90);
  71         }
  72 }
  73
  74 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  75 {
  76         /* Routing Table Node i
  77          *
  78          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  79          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  80          *
  81          * [ 0: 3] Request Route
  82          *     [0] Route to this node
  83          *     [1] Route to Link 0
  84          *     [2] Route to Link 1
  85          *     [3] Route to Link 2
  86          * [11: 8] Response Route
  87          *     [0] Route to this node
  88          *     [1] Route to Link 0
  89          *     [2] Route to Link 1
  90          *     [3] Route to Link 2
  91          * [19:16] Broadcast route
  92          *     [0] Route to this node
  93          *     [1] Route to Link 0
  94          *     [2] Route to Link 1
  95          *     [3] Route to Link 2
  96          */
  97
  98         uint32_t ret=0x00010101; /* default row entry */
  99
 100         static const unsigned int rows_2p[2][2] = {
 101                 { 0x00090101, 0x00010808 },
 102                 { 0x00010404, 0x00050101 }
 103         };
 104
 105         if(maxnodes > 2) {
 106                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 107                 maxnodes=2;
 108         }
 109
 110
 111         if (!(node >= maxnodes || row >= maxnodes)) {
 112                 ret=rows_2p[node][row];
 113         }
 114
 115         return ret;
 116 }
 117
 118 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 119 {
 120         /* nothing to do */
 121 }
 122
 123 static inline int spd_read_byte(unsigned device, unsigned address)
 124 {
 125         return smbus_read_byte(device, address);
 126 }
 127
 128 #include "northbridge/amd/amdk8/raminit.c"
 129
 130 #include "northbridge/amd/amdk8/coherent_ht.c"
 131
 132 #include "sdram/generic_sdram.c"
 133
 134 /* newisys khepri does not want the default */
 135 #include "resourcemap.c"
 136
 137 static void main(unsigned long bist)
 138 {
 139         static const struct mem_controller cpu[] = {
 140                 {
 141                         .node_id = 0,
 142                         .f0 = PCI_DEV(0, 0x18, 0),
 143                         .f1 = PCI_DEV(0, 0x18, 1),
 144                         .f2 = PCI_DEV(0, 0x18, 2),
 145                         .f3 = PCI_DEV(0, 0x18, 3),
 146                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 147                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 148                 },
 149                 {
 150                         .node_id = 1,
 151                         .f0 = PCI_DEV(0, 0x19, 0),
 152                         .f1 = PCI_DEV(0, 0x19, 1),
 153                         .f2 = PCI_DEV(0, 0x19, 2),
 154                         .f3 = PCI_DEV(0, 0x19, 3),
 155                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 156                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 157                 },
 158         };
 159
 160         int needs_reset;
 161         if (bist == 0) {
 162                 /* Skip this if there was a built in self test failure */
 163                 amd_early_mtrr_init();
 164                 enable_lapic();
 165                 init_timer();
 166                 /* Has this cpu already booted? */
 167                 if (cpu_init_detected()) {
 168                         asm volatile ("jmp __cpu_reset");
 169                 }
 170                 distinguish_cpu_resets();
 171                 if (!boot_cpu()) {
 172                         stop_this_cpu();
 173                 }
 174         }
 175         /* Setup the console */
 176         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 177         uart_init();
 178         console_init();
 179
 180         /* Halt if there was a built in self test failure */
 181         report_bist_failure(bist);
 182
 183         setup_khepri_resource_map();
 184         needs_reset = setup_coherent_ht_domain();
 185         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 186         if (needs_reset) {
 187                 print_info("ht reset -\r\n");
 188                 soft_reset();
 189         }
 190 #if 0
 191         print_pci_devices();
 192 #endif
 193         enable_smbus();
 194 #if 0
 195         dump_spd_registers(&cpu[0]);
 196 #endif
 197         memreset_setup();
 198         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 199
 200 #if 0
 201         dump_pci_devices();
 202 #endif
 203 #if 0
 204         dump_pci_device(PCI_DEV(0, 0x18, 2));
 205 #endif
 206
 207 #if 0
 208         /* Check the first 1M */
 209         ram_check(0x00000000, 0x000100000);
 210 #endif
 211 }