4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses LB_CKS_RANGE_START
34 uses MAINBOARD_PART_NUMBER
37 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
44 uses DEFAULT_CONSOLE_LOGLEVEL
45 uses MAXIMUM_CONSOLE_LOGLEVEL
46 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses HW_MEM_HOLE_SIZEK
63 uses CONFIG_USE_PRINTK_IN_CAR
70 ## ROM_SIZE is the size of boot ROM that this board will use.
72 default ROM_SIZE=524288
75 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
77 #default FALLBACK_SIZE=131072
79 default FALLBACK_SIZE=0x40000
82 ## Build code for the fallback boot
84 default HAVE_FALLBACK_BOOT=1
87 ## Build code to reset the motherboard from coreboot
89 default HAVE_HARD_RESET=1
92 ## Build code to export a programmable irq routing table
94 default HAVE_PIRQ_TABLE=1
95 default IRQ_SLOT_COUNT=15
98 ## Build code to export an x86 MP table
99 ## Useful for specifying IRQ routing values
101 default HAVE_MP_TABLE=1
104 ## Build code to export a CMOS option table
106 default HAVE_OPTION_TABLE=1
109 ## Move the default coreboot cmos range off of AMD RTC registers
111 default LB_CKS_RANGE_START=49
112 default LB_CKS_RANGE_END=122
113 default LB_CKS_LOC=123
116 ## Build code for SMP support
117 ## Only worry about 2 micro processors
120 default CONFIG_MAX_CPUS=4
121 default CONFIG_MAX_PHYSICAL_CPUS=2
122 default CONFIG_LOGICAL_CPUS=1
125 default CONFIG_CHIP_NAME=1
128 default HW_MEM_HOLE_SIZEK=0x100000
131 default CONFIG_CONSOLE_VGA=1
132 default CONFIG_PCI_ROM_RUN=1
136 ## enable CACHE_AS_RAM specifics
138 default USE_DCACHE_RAM=1
139 default DCACHE_RAM_BASE=0xcf000
140 default DCACHE_RAM_SIZE=0x1000
141 default CONFIG_USE_INIT=0
144 ## Build code to setup a generic IOAPIC
146 default CONFIG_IOAPIC=1
149 ## Clean up the motherboard id strings
151 default MAINBOARD_PART_NUMBER="Khepri"
152 default MAINBOARD_VENDOR="Newisys"
153 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
154 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
157 ### coreboot layout values
160 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
161 default ROM_IMAGE_SIZE = 65536
164 ## Use a small 8K stack
166 default STACK_SIZE=0x2000
169 ## Use a small 16K heap
171 default HEAP_SIZE=0x4000
174 ## Only use the option table in a normal image
176 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
179 ## Coreboot C code runs at this location in RAM
181 default _RAMBASE=0x00004000
184 ## Load the payload from the ROM
186 default CONFIG_ROM_PAYLOAD = 1
189 ### Defaults of options that you may want to override in the target config file
193 ## The default compiler
195 default CC="$(CROSS_COMPILE)gcc -m32"
199 ## Disable the gdb stub by default
201 default CONFIG_GDB_STUB=0
203 default CONFIG_USE_PRINTK_IN_CAR=1
206 ## The Serial Console
209 # To Enable the Serial Console
210 default CONFIG_CONSOLE_SERIAL8250=1
212 ## Select the serial console baud rate
213 default TTYS0_BAUD=115200
214 #default TTYS0_BAUD=57600
215 #default TTYS0_BAUD=38400
216 #default TTYS0_BAUD=19200
217 #default TTYS0_BAUD=9600
218 #default TTYS0_BAUD=4800
219 #default TTYS0_BAUD=2400
220 #default TTYS0_BAUD=1200
222 # Select the serial console base port
223 default TTYS0_BASE=0x3f8
225 # Select the serial protocol
226 # This defaults to 8 data bits, 1 stop bit, and no parity
227 default TTYS0_LCS=0x3
230 ### Select the coreboot loglevel
232 ## EMERG 1 system is unusable
233 ## ALERT 2 action must be taken immediately
234 ## CRIT 3 critical conditions
235 ## ERR 4 error conditions
236 ## WARNING 5 warning conditions
237 ## NOTICE 6 normal but significant condition
238 ## INFO 7 informational
239 ## DEBUG 8 debug-level messages
240 ## SPEW 9 Way too many details
242 ## Request this level of debugging output
243 default DEFAULT_CONSOLE_LOGLEVEL=8
244 ## At a maximum only compile in this level of debugging
245 default MAXIMUM_CONSOLE_LOGLEVEL=8
248 ## Select power on after power fail setting
249 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
256 default CONFIG_ROMFS=0