1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
14 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_IMAGE_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
24 uses CONFIG_PAYLOAD_SIZE
26 uses CONFIG_XIP_ROM_SIZE
27 uses CONFIG_XIP_ROM_BASE
28 uses CONFIG_STACK_SIZE
30 uses CONFIG_USE_OPTION_TABLE
31 uses CONFIG_LB_CKS_RANGE_START
32 uses CONFIG_LB_CKS_RANGE_END
33 uses CONFIG_LB_CKS_LOC
34 uses CONFIG_MAINBOARD_PART_NUMBER
35 uses CONFIG_MAINBOARD_VENDOR
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
41 uses CONFIG_TTYS0_BAUD
42 uses CONFIG_TTYS0_BASE
44 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
45 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
46 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
48 uses CONFIG_HAVE_INIT_TIMER
50 uses CONFIG_CROSS_COMPILE
54 uses CONFIG_CONSOLE_VGA
55 uses CONFIG_PCI_ROM_RUN
56 uses CONFIG_HW_MEM_HOLE_SIZEK
58 uses CONFIG_USE_DCACHE_RAM
59 uses CONFIG_DCACHE_RAM_BASE
60 uses CONFIG_DCACHE_RAM_SIZE
62 uses CONFIG_USE_PRINTK_IN_CAR
69 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
71 default CONFIG_ROM_SIZE=524288
74 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
76 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
79 ## Build code for the fallback boot
81 default CONFIG_HAVE_FALLBACK_BOOT=1
84 ## Build code to reset the motherboard from coreboot
86 default CONFIG_HAVE_HARD_RESET=1
89 ## Build code to export a programmable irq routing table
91 default CONFIG_HAVE_PIRQ_TABLE=1
92 default CONFIG_IRQ_SLOT_COUNT=15
95 ## Build code to export an x86 MP table
96 ## Useful for specifying IRQ routing values
98 default CONFIG_HAVE_MP_TABLE=1
101 ## Build code to export a CMOS option table
103 default CONFIG_HAVE_OPTION_TABLE=1
106 ## Move the default coreboot cmos range off of AMD RTC registers
108 default CONFIG_LB_CKS_RANGE_START=49
109 default CONFIG_LB_CKS_RANGE_END=122
110 default CONFIG_LB_CKS_LOC=123
113 ## Build code for SMP support
114 ## Only worry about 2 micro processors
117 default CONFIG_MAX_CPUS=4
118 default CONFIG_MAX_PHYSICAL_CPUS=2
119 default CONFIG_LOGICAL_CPUS=1
122 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
125 default CONFIG_CONSOLE_VGA=1
126 default CONFIG_PCI_ROM_RUN=1
130 ## enable CACHE_AS_RAM specifics
132 default CONFIG_USE_DCACHE_RAM=1
133 default CONFIG_DCACHE_RAM_BASE=0xcf000
134 default CONFIG_DCACHE_RAM_SIZE=0x1000
135 default CONFIG_USE_INIT=0
138 ## Build code to setup a generic IOAPIC
140 default CONFIG_IOAPIC=1
143 ## Clean up the motherboard id strings
145 default CONFIG_MAINBOARD_PART_NUMBER="Khepri"
146 default CONFIG_MAINBOARD_VENDOR="Newisys"
147 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
148 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
151 ### coreboot layout values
154 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
155 default CONFIG_ROM_IMAGE_SIZE = 65536
158 ## Use a small 8K stack
160 default CONFIG_STACK_SIZE=0x2000
163 ## Use a small 16K heap
165 default CONFIG_HEAP_SIZE=0x4000
168 ## Only use the option table in a normal image
170 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
173 ## Coreboot C code runs at this location in RAM
175 default CONFIG_RAMBASE=0x00004000
178 ## Load the payload from the ROM
180 default CONFIG_ROM_PAYLOAD = 1
183 ### Defaults of options that you may want to override in the target config file
187 ## The default compiler
189 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
193 ## Disable the gdb stub by default
195 default CONFIG_GDB_STUB=0
197 default CONFIG_USE_PRINTK_IN_CAR=1
200 ## The Serial Console
203 # To Enable the Serial Console
204 default CONFIG_CONSOLE_SERIAL8250=1
206 ## Select the serial console baud rate
207 default CONFIG_TTYS0_BAUD=115200
208 #default CONFIG_TTYS0_BAUD=57600
209 #default CONFIG_TTYS0_BAUD=38400
210 #default CONFIG_TTYS0_BAUD=19200
211 #default CONFIG_TTYS0_BAUD=9600
212 #default CONFIG_TTYS0_BAUD=4800
213 #default CONFIG_TTYS0_BAUD=2400
214 #default CONFIG_TTYS0_BAUD=1200
216 # Select the serial console base port
217 default CONFIG_TTYS0_BASE=0x3f8
219 # Select the serial protocol
220 # This defaults to 8 data bits, 1 stop bit, and no parity
221 default CONFIG_TTYS0_LCS=0x3
224 ### Select the coreboot loglevel
226 ## EMERG 1 system is unusable
227 ## ALERT 2 action must be taken immediately
228 ## CRIT 3 critical conditions
229 ## ERR 4 error conditions
230 ## WARNING 5 warning conditions
231 ## NOTICE 6 normal but significant condition
232 ## INFO 7 informational
233 ## CONFIG_DEBUG 8 debug-level messages
234 ## SPEW 9 Way too many details
236 ## Request this level of debugging output
237 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
238 ## At a maximum only compile in this level of debugging
239 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
242 ## Select power on after power fail setting
243 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
250 default CONFIG_CBFS=1