3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
18 uses ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
30 uses LB_CKS_RANGE_START
33 uses MAINBOARD_PART_NUMBER
36 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
43 uses DEFAULT_CONSOLE_LOGLEVEL
44 uses MAXIMUM_CONSOLE_LOGLEVEL
45 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
46 uses CONFIG_CONSOLE_SERIAL8250
54 uses CONFIG_CONSOLE_VGA
55 uses CONFIG_PCI_ROM_RUN
56 uses HW_MEM_HOLE_SIZEK
62 uses CONFIG_USE_PRINTK_IN_CAR
69 ## ROM_SIZE is the size of boot ROM that this board will use.
71 default ROM_SIZE=524288
74 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
76 #default FALLBACK_SIZE=131072
78 default FALLBACK_SIZE=0x40000
81 ## Build code for the fallback boot
83 default HAVE_FALLBACK_BOOT=1
86 ## Build code to reset the motherboard from coreboot
88 default HAVE_HARD_RESET=1
91 ## Build code to export a programmable irq routing table
93 default HAVE_PIRQ_TABLE=1
94 default IRQ_SLOT_COUNT=15
97 ## Build code to export an x86 MP table
98 ## Useful for specifying IRQ routing values
100 default HAVE_MP_TABLE=1
103 ## Build code to export a CMOS option table
105 default HAVE_OPTION_TABLE=1
108 ## Move the default coreboot cmos range off of AMD RTC registers
110 default LB_CKS_RANGE_START=49
111 default LB_CKS_RANGE_END=122
112 default LB_CKS_LOC=123
115 ## Build code for SMP support
116 ## Only worry about 2 micro processors
119 default CONFIG_MAX_CPUS=4
120 default CONFIG_MAX_PHYSICAL_CPUS=2
121 default CONFIG_LOGICAL_CPUS=1
124 default CONFIG_CHIP_NAME=1
127 default HW_MEM_HOLE_SIZEK=0x100000
130 default CONFIG_CONSOLE_VGA=1
131 default CONFIG_PCI_ROM_RUN=1
135 ## enable CACHE_AS_RAM specifics
137 default USE_DCACHE_RAM=1
138 default DCACHE_RAM_BASE=0xcf000
139 default DCACHE_RAM_SIZE=0x1000
140 default CONFIG_USE_INIT=0
143 ## Build code to setup a generic IOAPIC
145 default CONFIG_IOAPIC=1
148 ## Clean up the motherboard id strings
150 default MAINBOARD_PART_NUMBER="Khepri"
151 default MAINBOARD_VENDOR="Newisys"
152 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
153 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
156 ### coreboot layout values
159 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
160 default ROM_IMAGE_SIZE = 65536
163 ## Use a small 8K stack
165 default STACK_SIZE=0x2000
168 ## Use a small 16K heap
170 default HEAP_SIZE=0x4000
173 ## Only use the option table in a normal image
175 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
178 ## Coreboot C code runs at this location in RAM
180 default _RAMBASE=0x00004000
183 ## Load the payload from the ROM
185 default CONFIG_ROM_PAYLOAD = 1
188 ### Defaults of options that you may want to override in the target config file
192 ## The default compiler
194 default CC="$(CROSS_COMPILE)gcc -m32"
198 ## Disable the gdb stub by default
200 default CONFIG_GDB_STUB=0
202 default CONFIG_USE_PRINTK_IN_CAR=1
205 ## The Serial Console
208 # To Enable the Serial Console
209 default CONFIG_CONSOLE_SERIAL8250=1
211 ## Select the serial console baud rate
212 default TTYS0_BAUD=115200
213 #default TTYS0_BAUD=57600
214 #default TTYS0_BAUD=38400
215 #default TTYS0_BAUD=19200
216 #default TTYS0_BAUD=9600
217 #default TTYS0_BAUD=4800
218 #default TTYS0_BAUD=2400
219 #default TTYS0_BAUD=1200
221 # Select the serial console base port
222 default TTYS0_BASE=0x3f8
224 # Select the serial protocol
225 # This defaults to 8 data bits, 1 stop bit, and no parity
226 default TTYS0_LCS=0x3
229 ### Select the coreboot loglevel
231 ## EMERG 1 system is unusable
232 ## ALERT 2 action must be taken immediately
233 ## CRIT 3 critical conditions
234 ## ERR 4 error conditions
235 ## WARNING 5 warning conditions
236 ## NOTICE 6 normal but significant condition
237 ## INFO 7 informational
238 ## DEBUG 8 debug-level messages
239 ## SPEW 9 Way too many details
241 ## Request this level of debugging output
242 default DEFAULT_CONSOLE_LOGLEVEL=8
243 ## At a maximum only compile in this level of debugging
244 default MAXIMUM_CONSOLE_LOGLEVEL=8
247 ## Select power on after power fail setting
248 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"