3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
17 uses ROM_SECTION_OFFSET
18 uses CONFIG_ROM_STREAM
19 uses CONFIG_ROM_STREAM_START
20 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
28 uses LB_CKS_RANGE_START
31 uses MAINBOARD_PART_NUMBER
34 uses LINUXBIOS_EXTRA_VERSION
39 uses DEFAULT_CONSOLE_LOGLEVEL
40 uses MAXIMUM_CONSOLE_LOGLEVEL
41 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
42 uses CONFIG_CONSOLE_SERIAL8250
55 ## ROM_SIZE is the size of boot ROM that this board will use.
57 default ROM_SIZE=524288
60 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
62 default FALLBACK_SIZE=0x40000
65 ## Build code for the fallback boot
67 default HAVE_FALLBACK_BOOT=1
70 ## Build code to reset the motherboard from linuxBIOS
72 default HAVE_HARD_RESET=1
75 ## Build code to export a programmable irq routing table
77 default HAVE_PIRQ_TABLE=1
78 default IRQ_SLOT_COUNT=9
81 ## Build code to export an x86 MP table
82 ## Useful for specifying IRQ routing values
84 default HAVE_MP_TABLE=1
87 ## Build code to export a CMOS option table
89 default HAVE_OPTION_TABLE=1
92 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
94 default LB_CKS_RANGE_START=49
95 default LB_CKS_RANGE_END=122
96 default LB_CKS_LOC=123
99 ## Build code for SMP support
100 ## Only worry about 2 micro processors
103 default CONFIG_MAX_CPUS=2
104 default CONFIG_MAX_PHYSICAL_CPUS=2
107 ## Build code to setup a generic IOAPIC
109 default CONFIG_IOAPIC=1
112 ## Clean up the motherboard id strings
114 default MAINBOARD_PART_NUMBER="Khepri"
115 default MAINBOARD_VENDOR="Newisys"
118 ### LinuxBIOS layout values
121 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
122 default ROM_IMAGE_SIZE = 65536
125 ## Use a small 8K stack
127 default STACK_SIZE=0x2000
130 ## Use a small 16K heap
132 default HEAP_SIZE=0x4000
135 ## Only use the option table in a normal image
137 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
140 ## LinuxBIOS C code runs at this location in RAM
142 default _RAMBASE=0x00004000
145 ## Load the payload from the ROM
147 default CONFIG_ROM_STREAM = 1
150 ### Defaults of options that you may want to override in the target config file
154 ## The default compiler
156 default CC="$(CROSS_COMPILE)gcc -m32"
160 ## The Serial Console
163 # To Enable the Serial Console
164 default CONFIG_CONSOLE_SERIAL8250=1
166 ## Select the serial console baud rate
167 default TTYS0_BAUD=115200
168 #default TTYS0_BAUD=57600
169 #default TTYS0_BAUD=38400
170 #default TTYS0_BAUD=19200
171 #default TTYS0_BAUD=9600
172 #default TTYS0_BAUD=4800
173 #default TTYS0_BAUD=2400
174 #default TTYS0_BAUD=1200
176 # Select the serial console base port
177 default TTYS0_BASE=0x3f8
179 # Select the serial protocol
180 # This defaults to 8 data bits, 1 stop bit, and no parity
181 default TTYS0_LCS=0x3
184 ### Select the linuxBIOS loglevel
186 ## EMERG 1 system is unusable
187 ## ALERT 2 action must be taken immediately
188 ## CRIT 3 critical conditions
189 ## ERR 4 error conditions
190 ## WARNING 5 warning conditions
191 ## NOTICE 6 normal but significant condition
192 ## INFO 7 informational
193 ## DEBUG 8 debug-level messages
194 ## SPEW 9 Way too many details
196 ## Request this level of debugging output
197 default DEFAULT_CONSOLE_LOGLEVEL=8
198 ## At a maximum only compile in this level of debugging
199 default MAXIMUM_CONSOLE_LOGLEVEL=8
202 ## Select power on after power fail setting
203 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"