1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
13 uses CONFIG_FALLBACK_SIZE
15 uses CONFIG_ROM_SECTION_SIZE
16 uses CONFIG_ROM_IMAGE_SIZE
17 uses CONFIG_ROM_SECTION_SIZE
18 uses CONFIG_ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
23 uses CONFIG_PAYLOAD_SIZE
25 uses CONFIG_XIP_ROM_SIZE
26 uses CONFIG_XIP_ROM_BASE
27 uses CONFIG_STACK_SIZE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_LB_CKS_RANGE_START
31 uses CONFIG_LB_CKS_RANGE_END
32 uses CONFIG_LB_CKS_LOC
33 uses CONFIG_MAINBOARD_PART_NUMBER
34 uses CONFIG_MAINBOARD_VENDOR
36 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
40 uses CONFIG_TTYS0_BAUD
41 uses CONFIG_TTYS0_BASE
43 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
44 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
45 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
46 uses CONFIG_CONSOLE_SERIAL8250
47 uses CONFIG_HAVE_INIT_TIMER
49 uses CONFIG_CROSS_COMPILE
53 uses CONFIG_CONSOLE_VGA
54 uses CONFIG_PCI_ROM_RUN
55 uses CONFIG_HW_MEM_HOLE_SIZEK
57 uses CONFIG_USE_DCACHE_RAM
58 uses CONFIG_DCACHE_RAM_BASE
59 uses CONFIG_DCACHE_RAM_SIZE
61 uses CONFIG_USE_PRINTK_IN_CAR
68 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
70 default CONFIG_ROM_SIZE=524288
73 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
75 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
78 ## Build code for the fallback boot
80 default CONFIG_HAVE_FALLBACK_BOOT=1
83 ## Build code to reset the motherboard from coreboot
85 default CONFIG_HAVE_HARD_RESET=1
88 ## Build code to export a programmable irq routing table
90 default CONFIG_HAVE_PIRQ_TABLE=1
91 default CONFIG_IRQ_SLOT_COUNT=15
94 ## Build code to export an x86 MP table
95 ## Useful for specifying IRQ routing values
97 default CONFIG_HAVE_MP_TABLE=1
100 ## Build code to export a CMOS option table
102 default CONFIG_HAVE_OPTION_TABLE=1
105 ## Move the default coreboot cmos range off of AMD RTC registers
107 default CONFIG_LB_CKS_RANGE_START=49
108 default CONFIG_LB_CKS_RANGE_END=122
109 default CONFIG_LB_CKS_LOC=123
112 ## Build code for SMP support
113 ## Only worry about 2 micro processors
116 default CONFIG_MAX_CPUS=4
117 default CONFIG_MAX_PHYSICAL_CPUS=2
118 default CONFIG_LOGICAL_CPUS=1
121 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
124 default CONFIG_CONSOLE_VGA=1
125 default CONFIG_PCI_ROM_RUN=1
129 ## enable CACHE_AS_RAM specifics
131 default CONFIG_USE_DCACHE_RAM=1
132 default CONFIG_DCACHE_RAM_BASE=0xcf000
133 default CONFIG_DCACHE_RAM_SIZE=0x1000
134 default CONFIG_USE_INIT=0
137 ## Build code to setup a generic IOAPIC
139 default CONFIG_IOAPIC=1
142 ## Clean up the motherboard id strings
144 default CONFIG_MAINBOARD_PART_NUMBER="Khepri"
145 default CONFIG_MAINBOARD_VENDOR="Newisys"
146 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
147 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
150 ### coreboot layout values
153 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
154 default CONFIG_ROM_IMAGE_SIZE = 65536
157 ## Use a small 8K stack
159 default CONFIG_STACK_SIZE=0x2000
162 ## Use a small 16K heap
164 default CONFIG_HEAP_SIZE=0x4000
167 ## Only use the option table in a normal image
169 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
172 ## Coreboot C code runs at this location in RAM
174 default CONFIG_RAMBASE=0x00004000
177 ## Load the payload from the ROM
179 default CONFIG_ROM_PAYLOAD = 1
182 ### Defaults of options that you may want to override in the target config file
186 ## The default compiler
188 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
192 ## Disable the gdb stub by default
194 default CONFIG_GDB_STUB=0
196 default CONFIG_USE_PRINTK_IN_CAR=1
199 ## The Serial Console
202 # To Enable the Serial Console
203 default CONFIG_CONSOLE_SERIAL8250=1
205 ## Select the serial console baud rate
206 default CONFIG_TTYS0_BAUD=115200
207 #default CONFIG_TTYS0_BAUD=57600
208 #default CONFIG_TTYS0_BAUD=38400
209 #default CONFIG_TTYS0_BAUD=19200
210 #default CONFIG_TTYS0_BAUD=9600
211 #default CONFIG_TTYS0_BAUD=4800
212 #default CONFIG_TTYS0_BAUD=2400
213 #default CONFIG_TTYS0_BAUD=1200
215 # Select the serial console base port
216 default CONFIG_TTYS0_BASE=0x3f8
218 # Select the serial protocol
219 # This defaults to 8 data bits, 1 stop bit, and no parity
220 default CONFIG_TTYS0_LCS=0x3
223 ### Select the coreboot loglevel
225 ## EMERG 1 system is unusable
226 ## ALERT 2 action must be taken immediately
227 ## CRIT 3 critical conditions
228 ## ERR 4 error conditions
229 ## WARNING 5 warning conditions
230 ## NOTICE 6 normal but significant condition
231 ## INFO 7 informational
232 ## CONFIG_DEBUG 8 debug-level messages
233 ## SPEW 9 Way too many details
235 ## Request this level of debugging output
236 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
237 ## At a maximum only compile in this level of debugging
238 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
241 ## Select power on after power fail setting
242 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"