1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
6 ## Set all of the defaults for an x86 architecture
12 ## Build the objects we have code for in this directory.
16 if CONFIG_GENERATE_MP_TABLE object mptable.o end
17 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
22 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
23 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
29 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
30 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
31 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
32 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
38 ## Build our 16 bit and 32 bit coreboot entry code
40 if CONFIG_USE_FALLBACK_IMAGE
41 mainboardinit cpu/x86/16bit/entry16.inc
42 ldscript /cpu/x86/16bit/entry16.lds
45 mainboardinit cpu/x86/32bit/entry32.inc
48 ldscript /cpu/x86/32bit/entry32.lds
52 ldscript /cpu/amd/car/cache_as_ram.lds
56 ## Build our reset vector (This is where coreboot is entered)
58 if CONFIG_USE_FALLBACK_IMAGE
59 mainboardinit cpu/x86/16bit/reset16.inc
60 ldscript /cpu/x86/16bit/reset16.lds
62 mainboardinit cpu/x86/32bit/reset32.inc
63 ldscript /cpu/x86/32bit/reset32.lds
67 ## Include an id string (For safe flashing)
69 mainboardinit arch/i386/lib/id.inc
70 ldscript /arch/i386/lib/id.lds
75 mainboardinit cpu/amd/car/cache_as_ram.inc
78 ### This is the early phase of coreboot startup
79 ### Things are delicate and we test to see if we should
80 ### failover to another image.
82 if CONFIG_USE_FALLBACK_IMAGE
83 ldscript /arch/i386/lib/failover.lds
87 ### O.k. We aren't just an intermediary anymore!
96 mainboardinit ./auto.inc
101 chip northbridge/amd/amdk8/root_complex
102 device apic_cluster 0 on
103 chip cpu/amd/socket_940
106 chip cpu/amd/socket_940
111 device pci_domain 0 on
112 chip northbridge/amd/amdk8
113 device pci 18.0 on end # LDT 0
114 device pci 18.0 on # LDT 1
115 chip southbridge/amd/amd8131
116 device pci 0.0 on end
117 device pci 0.1 on end
118 device pci 1.0 on end
119 device pci 1.1 on end
121 chip southbridge/amd/amd8111
123 device pci 0.0 on end
124 device pci 0.1 on end
125 device pci 0.2 on end
126 device pci 1.0 on end
129 chip superio/winbond/w83627hf
130 device pnp 2e.0 on # Floppy
135 device pnp 2e.1 off # Parallel Port
139 device pnp 2e.2 on # Com1
143 device pnp 2e.3 on # Com2
147 device pnp 2e.5 on # Keyboard
153 device pnp 2e.6 off # CIR
156 device pnp 2e.7 off # GAME_MIDI_GIPO1
161 device pnp 2e.8 off end # GPIO2
162 device pnp 2e.9 off end # GPIO3
163 device pnp 2e.a off end # ACPI
164 device pnp 2e.b on # HW Monitor
170 device pci 1.1 on end
171 device pci 1.2 on end
172 device pci 1.3 on end
173 device pci 1.5 on end
174 device pci 1.6 on end
177 device pci 18.0 on end # LDT2
178 device pci 18.1 on end
179 device pci 18.2 on end
180 device pci 18.3 on end
182 chip northbridge/amd/amdk8
183 device pci 19.0 on end
184 device pci 19.0 on end
185 device pci 19.0 on end
186 device pci 19.1 on end
187 device pci 19.2 on end
188 device pci 19.3 on end