src/mainboard/newisys/khepri/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 ##
  36 ## Set all of the defaults for an x86 architecture
  37 ##
  38
  39 arch i386 end
  40
  41 ##
  42 ## Build the objects we have code for in this directory.
  43 ##
  44
  45 driver mainboard.o
  46 if HAVE_MP_TABLE object mptable.o end
  47 if HAVE_PIRQ_TABLE object irq_tables.o end
  48 #object reset.o
  49
  50 dir /drivers/trident/blade3d
  51
  52 ##
  53 ## Romcc output
  54 ##
  55 makerule ./failover.E
  56         depends "$(MAINBOARD)/failover.c ./romcc"
  57         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  58 end
  59
  60 makerule ./failover.inc
  61         depends "$(MAINBOARD)/failover.c ./romcc"
  62         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  63 end
  64
  65 makerule ./auto.E
  66         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  67         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  68 end
  69 makerule ./auto.inc
  70         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  71         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  72 end
  73
  74 ##
  75 ## Build our 16 bit and 32 bit linuxBIOS entry code
  76 ##
  77 mainboardinit cpu/x86/16bit/entry16.inc
  78 mainboardinit cpu/x86/32bit/entry32.inc
  79 ldscript /cpu/x86/16bit/entry16.lds
  80 ldscript /cpu/x86/32bit/entry32.lds
  81
  82 ##
  83 ## Build our reset vector (This is where linuxBIOS is entered)
  84 ##
  85 if USE_FALLBACK_IMAGE
  86         mainboardinit cpu/x86/16bit/reset16.inc
  87         ldscript /cpu/x86/16bit/reset16.lds
  88 else
  89         mainboardinit cpu/x86/32bit/reset32.inc
  90         ldscript /cpu/x86/32bit/reset32.lds
  91 end
  92
  93 ### Should this be in the northbridge code?
  94 mainboardinit arch/i386/lib/cpu_reset.inc
  95
  96 ##
  97 ## Include an id string (For safe flashing)
  98 ##
  99 mainboardinit arch/i386/lib/id.inc
 100 ldscript /arch/i386/lib/id.lds
 101
 102 ###
 103 ### This is the early phase of linuxBIOS startup
 104 ### Things are delicate and we test to see if we should
 105 ### failover to another image.
 106 ###
 107 if USE_FALLBACK_IMAGE
 108         ldscript /arch/i386/lib/failover.lds
 109         mainboardinit ./failover.inc
 110 end
 111
 112 ###
 113 ### O.k. We aren't just an intermediary anymore!
 114 ###
 115
 116 ##
 117 ## Setup RAM
 118 ##
 119 mainboardinit cpu/x86/fpu/enable_fpu.inc
 120 mainboardinit cpu/x86/mmx/enable_mmx.inc
 121 mainboardinit cpu/x86/sse/enable_sse.inc
 122 mainboardinit ./auto.inc
 123 mainboardinit cpu/x86/sse/disable_sse.inc
 124 mainboardinit cpu/x86/mmx/disable_mmx.inc
 125
 126 ##
 127 ## Include the secondary Configuration files
 128 ##
 129 dir /pc80
 130 config chip.h
 131
 132 chip northbridge/amd/amdk8/root_complex
 133         device pci_domain 0 on
 134                 chip northbridge/amd/amdk8
 135                         device pci 18.0 on end # LDT 0
 136                         device pci 18.0 on     # LDT 1
 137                                 chip southbridge/amd/amd8131
 138                                         device pci 0.0 on end
 139                                         device pci 0.1 on end
 140                                         device pci 1.0 on end
 141                                         device pci 1.1 on end
 142                                 end
 143                                 chip southbridge/amd/amd8111
 144                                         device pci 0.0 on
 145                                                 device pci 0.0 on end
 146                                                 device pci 0.1 on end
 147                                                 device pci 0.2 on end
 148                                                 device pci 1.0 on end
 149                                         end
 150                                         device pci 1.0 on
 151                                                 chip superio/nsc/pc87360
 152                                                         device pnp 2e.0 off    # Floppy
 153                                                                  io 0x60 = 0x3f0
 154                                                                 irq 0x70 = 6
 155                                                                 drq 0x74 = 2
 156                                                         end
 157                                                         device pnp 2e.1 off     # Parallel Port
 158                                                                  io 0x60 = 0x378
 159                                                                 irq 0x70 = 7
 160                                                         end
 161                                                         device pnp 2e.2 off     # Com 2
 162                                                                  io 0x60 = 0x2f8
 163                                                                 irq 0x70 = 3
 164                                                         end
 165                                                         device pnp 2e.3 on      # Com 1
 166                                                                  io 0x60 = 0x3f8
 167                                                                 irq 0x70 = 4
 168                                                         end
 169                                                         device pnp 2e.4 off end # SWC
 170                                                         device pnp 2e.5 off end # Mouse
 171                                                         device pnp 2e.6 on      # Keyboard
 172                                                                  io 0x60 = 0x60
 173                                                                  io 0x62 = 0x64
 174                                                                 irq 0x70 = 1
 175                                                         end
 176                                                         device pnp 2e.7 off end # GPIO
 177                                                         device pnp 2e.8 off end # ACB
 178                                                         device pnp 2e.9 off end # FSCM
 179                                                         device pnp 2e.a off end # WDT
 180
 181                                                 end
 182                                         end
 183                                         device pci 1.1 on end
 184                                         device pci 1.2 on end
 185                                         device pci 1.3 on end
 186                                         device pci 1.5 on end
 187                                         device pci 1.6 on end
 188                                 end
 189                         end # LDT1
 190                         device pci 18.0 on end # LDT2
 191                         device pci 18.1 on end
 192                         device pci 18.2 on end
 193                         device pci 18.3 on end
 194                 end
 195                 chip northbridge/amd/amdk8
 196                         device pci 19.0 on end
 197                         device pci 19.0 on end
 198                         device pci 19.0 on end
 199                         device pci 19.1 on end
 200                         device pci 19.2 on end
 201                         device pci 19.3 on end
 202                 end
 203         end
 204         device apic_cluster 0 on
 205                 chip cpu/amd/socket_940
 206                         device apic 0 on end
 207                 end
 208                 chip cpu/amd/socket_940
 209                         device apic 1 on end
 210                 end
 211         end
 212 end
 213