2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 default ROM_SECTION_SIZE = FALLBACK_SIZE
23 default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
25 default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
26 default ROM_SECTION_OFFSET = 0
28 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
29 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
30 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
31 default XIP_ROM_SIZE = 64 * 1024
32 default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
35 if HAVE_PIRQ_TABLE object irq_tables.o end
38 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
39 action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
41 makerule ./failover.inc
42 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
43 action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
46 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
47 depends "$(MAINBOARD)/auto.c ../romcc"
48 action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
51 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
52 depends "$(MAINBOARD)/auto.c ../romcc"
53 action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
55 mainboardinit cpu/x86/16bit/entry16.inc
56 mainboardinit cpu/x86/32bit/entry32.inc
57 ldscript /cpu/x86/16bit/entry16.lds
58 ldscript /cpu/x86/32bit/entry32.lds
60 mainboardinit cpu/x86/16bit/reset16.inc
61 ldscript /cpu/x86/16bit/reset16.lds
63 mainboardinit cpu/x86/32bit/reset32.inc
64 ldscript /cpu/x86/32bit/reset32.lds
66 mainboardinit arch/i386/lib/cpu_reset.inc
67 mainboardinit arch/i386/lib/id.inc
68 ldscript /arch/i386/lib/id.lds
70 ldscript /arch/i386/lib/failover.lds
71 mainboardinit ./failover.inc
73 mainboardinit cpu/x86/fpu/enable_fpu.inc
74 mainboardinit cpu/x86/mmx/enable_mmx.inc
75 mainboardinit ./auto.inc
76 mainboardinit cpu/x86/mmx/disable_mmx.inc
80 chip northbridge/intel/i82810 # Northbridge
81 device apic_cluster 0 on # APIC cluster
82 chip cpu/intel/socket_PGA370 # CPU
83 device apic 0 on end # APIC
86 device pci_domain 0 on
87 device pci 0.0 on end # Host bridge
88 device pci 1.0 off # Onboard video
89 # chip drivers/pci/onboard
90 # device pci 1.0 on end
91 # register "rom_address" = "0xfff80000"
94 chip southbridge/intel/i82801xx # Southbridge
95 device pci 1e.0 on end # PCI bridge
96 device pci 1f.0 on # ISA/LPC bridge
97 chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x)
98 device pnp 2e.0 on # Floppy
103 device pnp 2e.3 on # Parallel port
108 device pnp 2e.4 on # Com1
112 device pnp 2e.5 off end # Com2 (N/A)
113 device pnp 2e.7 on # PS/2 keyboard
117 device pnp 2e.9 off end # Game port (N/A)
118 device pnp 2e.a on # Power-management events (PME)
121 device pnp 2e.b on # MIDI port
127 device pci 1f.1 on end # IDE
128 device pci 1f.2 on end # USB
129 device pci 1f.3 on end # SMBus
130 device pci 1f.5 on end # AC'97 audio
131 device pci 1f.6 off end # AC'97 modem (N/A)