src/mainboard/msi/ms9652_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #define ASSEMBLY 1
  23 #define __PRE_RAM__
  24
  25 #define RAMINIT_SYSINFO 1
  26
  27 #define FAM10_SCAN_PCI_BUS 0
  28 #define FAM10_ALLOCATE_IO_RANGE 1
  29
  30 #define QRANK_DIMM_SUPPORT 1
  31
  32 #if CONFIG_LOGICAL_CPUS==1
  33 #define SET_NB_CFG_54 1
  34 #endif
  35
  36 #define FAM10_SET_FIDVID 1
  37 #define FAM10_SET_FIDVID_CORE_RANGE 0
  38
  39 #define DBGP_DEFAULT 7
  40
  41 #include <stdint.h>
  42 #include <string.h>
  43 #include <device/pci_def.h>
  44 #include <device/pci_ids.h>
  45 #include <arch/io.h>
  46 #include <device/pnp_def.h>
  47 #include <arch/romcc_io.h>
  48 #include <cpu/x86/lapic.h>
  49 #include "option_table.h"
  50 #include "pc80/mc146818rtc_early.c"
  51 #include "pc80/serial.c"
  52
  53 static void post_code(u8 value) {
  54         outb(value, 0x80);
  55 }
  56
  57 #if CONFIG_USE_FAILOVER_IMAGE==0
  58 #include "arch/i386/lib/console.c"
  59 #if CONFIG_USBDEBUG_DIRECT
  60 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
  61 #include "pc80/usbdebug_direct_serial.c"
  62 #endif
  63 #include "lib/ramtest.c"
  64
  65 #include <cpu/amd/model_10xxx_rev.h>
  66
  67 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  68 #include "northbridge/amd/amdfam10/raminit.h"
  69 #include "northbridge/amd/amdfam10/amdfam10.h"
  70
  71 #endif
  72
  73 #include "cpu/x86/lapic/boot_cpu.c"
  74 #include "northbridge/amd/amdfam10/reset_test.c"
  75 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  76
  77 #if CONFIG_USE_FAILOVER_IMAGE==0
  78
  79 #include "cpu/x86/bist.h"
  80
  81 #include "northbridge/amd/amdfam10/debug.c"
  82
  83 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  84
  85 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  86
  87 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  88 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  89
  90 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  91
  92 static void memreset_setup(void)
  93 {
  94 }
  95
  96 static void memreset(int controllers, const struct mem_controller *ctrl)
  97 {
  98 }
  99
 100 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 101 {
 102         /* nothing to do */
 103 }
 104
 105 static inline int spd_read_byte(unsigned device, unsigned address)
 106 {
 107         return smbus_read_byte(device, address);
 108 }
 109
 110 #include "northbridge/amd/amdfam10/amdfam10.h"
 111 #include "northbridge/amd/amdht/ht_wrapper.c"
 112
 113 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 114 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
 115 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
 116
 117 #include "resourcemap.c"
 118
 119 #include "cpu/amd/quadcore/quadcore.c"
 120
 121 #define MCP55_NUM 1
 122 #define MCP55_USE_NIC 1
 123 #define MCP55_USE_AZA 1
 124
 125 #define MCP55_PCI_E_X_0 1
 126
 127 #define MCP55_MB_SETUP \
 128         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
 129         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
 130         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
 131         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
 132         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
 133         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 134
 135 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 136 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 137
 138 #include "cpu/amd/car/copy_and_run.c"
 139
 140 #include "cpu/amd/car/post_cache_as_ram.c"
 141
 142 #include "cpu/amd/model_10xxx/init_cpus.c"
 143
 144 #include "cpu/amd/model_10xxx/fidvid.c"
 145
 146 #endif
 147
 148 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 149 #include "northbridge/amd/amdfam10/early_ht.c"
 150
 151 static void sio_setup(void)
 152 {
 153         unsigned value;
 154         uint32_t dword;
 155         uint8_t byte;
 156
 157         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 158         byte |= 0x20;
 159         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 160
 161         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 162         dword |= (1<<0);
 163         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 164 }
 165
 166 #if CONFIG_USE_FAILOVER_IMAGE==0
 167 #include "spd_addr.h"
 168 #include "cpu/amd/microcode/microcode.c"
 169 #include "cpu/amd/model_10xxx/update_microcode.c"
 170
 171 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 172 {
 173         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 174
 175         u32 bsp_apicid = 0;
 176         u32 val;
 177         u8 reg;
 178         u32 wants_reset;
 179         msr_t msr;
 180
 181         if (!((cpu_init_detectedx) || (!boot_cpu()))) {
 182                 /* Nothing special needs to be done to find bus 0 */
 183                 /* Allow the HT devices to be found */
 184
 185                 set_bsp_node_CHtExtNodeCfgEn();
 186                 enumerate_ht_chain();
 187
 188                 sio_setup();
 189
 190                 /* Setup the mcp55 */
 191                 mcp55_enable_rom();
 192         }
 193
 194         post_code(0x30);
 195
 196         if (bist == 0) {
 197                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 198         }
 199
 200         post_code(0x32);
 201
 202         pnp_enter_ext_func_mode(SERIAL_DEV);
 203         /* We have 24MHz input. */
 204         reg = pnp_read_config(SERIAL_DEV, 0x24);
 205         pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
 206         pnp_exit_ext_func_mode(SERIAL_DEV);
 207
 208         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 209         uart_init();
 210         console_init();
 211         printk_debug("\n");
 212
 213         /* Halt if there was a built in self test failure */
 214         report_bist_failure(bist);
 215
 216 #if CONFIG_USBDEBUG_DIRECT
 217         mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
 218         early_usbdebug_direct_init();
 219 #endif
 220
 221         val = cpuid_eax(1);
 222         printk_debug("BSP Family_Model: %08x\n", val);
 223         printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
 224         printk_debug("bsp_apicid = %02x\n", bsp_apicid);
 225         printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);
 226
 227         /* Setup sysinfo defaults */
 228         set_sysinfo_in_ram(0);
 229
 230         update_microcode(val);
 231         post_code(0x33);
 232
 233         cpuSetAMDMSR();
 234         post_code(0x34);
 235
 236         amd_ht_init(sysinfo);
 237         post_code(0x35);
 238
 239         /* Setup nodes PCI space and start core 0 AP init. */
 240         finalize_node_setup(sysinfo);
 241         printk_debug("finalize_node_setup done\n");
 242
 243         /* Setup any mainboard PCI settings etc. */
 244         printk_debug("setup_mb_resource_map begin\n");
 245         setup_mb_resource_map();
 246         printk_debug("setup_mb_resource_map end\n");
 247         post_code(0x36);
 248
 249         /* wait for all the APs core0 started by finalize_node_setup. */
 250         /* FIXME: A bunch of cores are going to start output to serial at once.
 251          * It would be nice to fixup prink spinlocks for ROM XIP mode.
 252          * I think it could be done by putting the spinlock flag in the cache
 253          * of the BSP located right after sysinfo.
 254          */
 255         wait_all_core0_started();
 256
 257 #if CONFIG_LOGICAL_CPUS==1
 258         /* Core0 on each node is configured. Now setup any additional cores. */
 259         printk_debug("start_other_cores()\n");
 260         start_other_cores();
 261         post_code(0x37);
 262         printk_debug("wait_all_other_cores_started()\n");
 263         wait_all_other_cores_started(bsp_apicid);
 264 #endif
 265
 266         post_code(0x38);
 267
 268 #if FAM10_SET_FIDVID == 1
 269         msr = rdmsr(0xc0010071);
 270         printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 271
 272         /* FIXME: The sb fid change may survive the warm reset and only
 273          * need to be done once.*/
 274         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 275
 276         post_code(0x39);
 277
 278         if (!warm_reset_detect(0)) {                    // BSP is node 0
 279                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 280         } else {
 281                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 282         }
 283
 284         post_code(0x3A);
 285
 286         /* show final fid and vid */
 287         msr=rdmsr(0xc0010071);
 288         printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 289 #endif
 290
 291         wants_reset = mcp55_early_setup_x();
 292
 293         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 294         if (!warm_reset_detect(0)) {
 295                 print_info("...WARM RESET...\n\n\n");
 296                 soft_reset();
 297                 die("After soft_reset_x - shouldn't see this message!!!\n");
 298         }
 299
 300         if (wants_reset)
 301                 printk_debug("mcp55_early_setup_x wanted additional reset!\n");
 302
 303         post_code(0x3B);
 304
 305         /* It's the time to set ctrl in sysinfo now; */
 306         printk_debug("fill_mem_ctrl()\n");
 307         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 308         post_code(0x3D);
 309
 310         printk_debug("enable_smbus()\n");
 311         enable_smbus();
 312         post_code(0x3E);
 313
 314         memreset_setup();
 315         post_code(0x40);
 316
 317         printk_debug("raminit_amdmct()\n");
 318         raminit_amdmct(sysinfo);
 319         post_code(0x41);
 320
 321         printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
 322         post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
 323         post_code(0x43);        // Should never see this post code.
 324 }
 325
 326
 327 #endif