2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define RAMINIT_SYSINFO 1
24 #define FAM10_SCAN_PCI_BUS 0
25 #define FAM10_ALLOCATE_IO_RANGE 1
27 #define QRANK_DIMM_SUPPORT 1
29 #if CONFIG_LOGICAL_CPUS==1
30 #define SET_NB_CFG_54 1
34 #define SET_FIDVID_CORE_RANGE 0
36 #define DBGP_DEFAULT 7
40 #include <device/pci_def.h>
41 #include <device/pci_ids.h>
43 #include <device/pnp_def.h>
44 #include <arch/romcc_io.h>
45 #include <cpu/x86/lapic.h>
46 #include "option_table.h"
47 #include "pc80/mc146818rtc_early.c"
48 #include "pc80/serial.c"
49 #include "console/console.c"
50 #if CONFIG_USBDEBUG_DIRECT
51 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
52 #include "pc80/usbdebug_direct_serial.c"
54 #include "lib/ramtest.c"
56 #include <cpu/amd/model_10xxx_rev.h>
58 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
59 #include "northbridge/amd/amdfam10/raminit.h"
60 #include "northbridge/amd/amdfam10/amdfam10.h"
62 #include "cpu/x86/lapic/boot_cpu.c"
63 #include "northbridge/amd/amdfam10/reset_test.c"
64 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
66 #include "cpu/x86/bist.h"
68 #include "northbridge/amd/amdfam10/debug.c"
70 #include "cpu/amd/mtrr/amd_earlymtrr.c"
72 #include "northbridge/amd/amdfam10/setup_resource_map.c"
74 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
75 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
77 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
79 static void memreset_setup(void)
83 static void memreset(int controllers, const struct mem_controller *ctrl)
87 static inline void activate_spd_rom(const struct mem_controller *ctrl)
92 static inline int spd_read_byte(unsigned device, unsigned address)
94 return smbus_read_byte(device, address);
97 #include "northbridge/amd/amdfam10/amdfam10.h"
98 #include "northbridge/amd/amdht/ht_wrapper.c"
100 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
101 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
102 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
104 #include "resourcemap.c"
106 #include "cpu/amd/quadcore/quadcore.c"
109 #define MCP55_USE_NIC 1
110 #define MCP55_USE_AZA 1
112 #define MCP55_PCI_E_X_0 1
114 #define MCP55_MB_SETUP \
115 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
116 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
117 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
118 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
119 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
120 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
122 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
123 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
125 #include "cpu/amd/car/copy_and_run.c"
127 #include "cpu/amd/car/post_cache_as_ram.c"
129 #include "cpu/amd/model_10xxx/init_cpus.c"
131 #include "cpu/amd/model_10xxx/fidvid.c"
133 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
134 #include "northbridge/amd/amdfam10/early_ht.c"
136 static void sio_setup(void)
141 byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
143 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
145 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
147 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
150 #include "spd_addr.h"
151 #include "cpu/amd/microcode/microcode.c"
152 #include "cpu/amd/model_10xxx/update_microcode.c"
154 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
156 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
164 if (!cpu_init_detectedx && boot_cpu()) {
165 /* Nothing special needs to be done to find bus 0 */
166 /* Allow the HT devices to be found */
168 set_bsp_node_CHtExtNodeCfgEn();
169 enumerate_ht_chain();
173 /* Setup the mcp55 */
180 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
185 pnp_enter_ext_func_mode(SERIAL_DEV);
186 /* We have 24MHz input. */
187 reg = pnp_read_config(SERIAL_DEV, 0x24);
188 pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
189 pnp_exit_ext_func_mode(SERIAL_DEV);
191 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
194 printk(BIOS_DEBUG, "\n");
196 /* Halt if there was a built in self test failure */
197 report_bist_failure(bist);
199 #if CONFIG_USBDEBUG_DIRECT
200 mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
201 early_usbdebug_direct_init();
205 printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
206 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
207 printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
208 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
210 /* Setup sysinfo defaults */
211 set_sysinfo_in_ram(0);
213 update_microcode(val);
219 amd_ht_init(sysinfo);
222 /* Setup nodes PCI space and start core 0 AP init. */
223 finalize_node_setup(sysinfo);
224 printk(BIOS_DEBUG, "finalize_node_setup done\n");
226 /* Setup any mainboard PCI settings etc. */
227 printk(BIOS_DEBUG, "setup_mb_resource_map begin\n");
228 setup_mb_resource_map();
229 printk(BIOS_DEBUG, "setup_mb_resource_map end\n");
232 /* wait for all the APs core0 started by finalize_node_setup. */
233 /* FIXME: A bunch of cores are going to start output to serial at once.
234 * It would be nice to fixup prink spinlocks for ROM XIP mode.
235 * I think it could be done by putting the spinlock flag in the cache
236 * of the BSP located right after sysinfo.
238 wait_all_core0_started();
240 #if CONFIG_LOGICAL_CPUS==1
241 /* Core0 on each node is configured. Now setup any additional cores. */
242 printk(BIOS_DEBUG, "start_other_cores()\n");
245 printk(BIOS_DEBUG, "wait_all_other_cores_started()\n");
246 wait_all_other_cores_started(bsp_apicid);
252 msr = rdmsr(0xc0010071);
253 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
255 /* FIXME: The sb fid change may survive the warm reset and only
256 * need to be done once.*/
257 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
261 if (!warm_reset_detect(0)) { // BSP is node 0
262 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
264 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
269 /* show final fid and vid */
270 msr=rdmsr(0xc0010071);
271 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
274 wants_reset = mcp55_early_setup_x();
276 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
277 if (!warm_reset_detect(0)) {
278 print_info("...WARM RESET...\n\n\n");
280 die("After soft_reset_x - shouldn't see this message!!!\n");
284 printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
288 /* It's the time to set ctrl in sysinfo now; */
289 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
290 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
293 printk(BIOS_DEBUG, "enable_smbus()\n");
300 printk(BIOS_DEBUG, "raminit_amdmct()\n");
301 raminit_amdmct(sysinfo);
304 printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
305 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
306 post_code(0x43); // Should never see this post code.